Abstract: According to one embodiment, a program causes a processor to perform providing, by a fault injection module, cooperation information to a debug function. The program causes a processor to perform receiving, by the fault injection module, a notification of at least one of condition related information and action related information as a response to the cooperation information from the debug function. The program causes a processor to perform determining, by the fault injection module, at least one of a fault injection condition and a fault injection action based on the notification. The program causes a processor to perform creating, by the fault injection module, a fault injection scenario that defines a fault injection procedure with respect to the fault injection target based on at least one of the determined fault injection condition and fault injection action.

Abstract: In an embodiment, a device includes a first unit, a second unit, and a third unit. The first unit generates a write address representing a write position to sequentially store sequential data from a processor to a nonvolatile main memory. The second unit generates order information representing a degree of newness of write. The third unit writes sequentially writes the sequential data at the write address with the order information.

Abstract: An information processing device of an example of the invention comprises an address generation section that generates a write address indicating a write position in a nonvolatile memory so that the write position is shifted in order to suppress each number of times of overlapped writing for each position of the nonvolatile memory when a write operation to the nonvolatile memory from a processor is performed, an order generation section that generates order information indicating a generation order of the writing operation, and a write control section that stores write information to the write address, and stores the order information to the nonvolatile memory so that the order information is related to at least one of the stored write information and the write address.

Abstract: An information processing device of an example of the invention comprises an address generation section that generates a write address indicating a write position in a nonvolatile memory so that the write position is shifted in order to suppress each number of times of overlapped writing for each position of the nonvolatile memory when a write operation to the nonvolatile memory from a processor is performed, an order generation section that generates order information indicating a generation order of the writing operation, and a write control section that stores write information to the write address, and stores the order information to the nonvolatile memory so that the order information is related to at least one of the stored write information and the write address.

Abstract: Systems and methods for efficiently switching context between processing elements are disclosed. These systems and methods may transfer the context of a processing element to a storage location. Using the DMA controller of a target processing element, the contents of this storage location may be transferred to another storage location associated with the target processing element. The context may then be restored from this storage location to the proper locations in the target processing element, and the target processing element may then begin processing utilizing this transferred context.

Abstract: Systems and methods for sensing temperatures of multiple functional blocks within a digital device and controlling the operation of these functional blocks in a manner that selectively reduces temperatures associated with some of the functional blocks, but not others. One embodiment comprises an integrated circuit having multiple functional blocks (such as processor cores) and a set of thermal sensors coupled to sense the temperatures of the functional blocks. The integrated circuit includes control circuitry configured to receive signals from the thermal sensors, detect thermal events in the functional blocks and to individually adjust operation of the functional blocks to reduce the temperatures causing the thermal events. In one embodiment, the control circuitry includes a detection/control circuit coupled to each of the functional blocks and a thermal management unit configured to evaluate detected thermal events and to determine actions to be taken in response to the thermal events.

Abstract: Systems and methods for efficiently switching context between processing elements are disclosed. These systems and methods may transfer the context of a processing element to a storage location. Using the DMA controller of a target processing element, the contents of this storage location may be transferred to another storage location associated with the target processing element. The context may then be restored from this storage location to the proper locations in the target processing element, and the target processing element may then begin processing utilizing this transferred context.

Abstract: Systems and methods for sensing temperatures of multiple functional blocks within a digital device and controlling the operation of these functional blocks in a manner that selectively reduces temperatures associated with some of the functional blocks, but not others. One embodiment comprises an integrated circuit having multiple functional blocks (such as processor cores) and a set of thermal sensors coupled to sense the temperatures of the functional blocks. The integrated circuit includes control circuitry configured to receive signals from the thermal sensors, detect thermal events in the functional blocks and to individually adjust operation of the functional blocks to reduce the temperatures causing the thermal events. In one embodiment, the control circuitry includes a detection/control circuit coupled to each of the functional blocks and a thermal management unit configured to evaluate detected thermal events and to determine actions to be taken in response to the thermal events.

Abstract: A computer system capable of system management from a terminal having a wireless communication function is provided with an IrDA-IF having an IrDA port capable of infrared wireless communication between the terminal and the computer system itself and a system management controller connected to the IrDA-IF, the system management controller performing the system management instructed by the terminal through infrared wireless communication with the terminal through the IrDA-IF.

Abstract: In a computer system, a control signal line directly connecting a processor to a power sequence controller is provided and a PSC interface for exchanging a control signal with the power sequence controller is built in the processor. When all the devices connected to a specific IO bus have been out of use for a long time, the processor transmits a control signal to stop the supply of power to the IO bus to the power sequence controller. This stops power from being supplied to not only the devices connected to the IO bus but also the IO bus. As a result, the unnecessarily consumed power in the computer system is reduced remarkably.

Abstract: A distributed shared-memory multiprocessor system capable of reducing a traffic on the shared bus, without imposing any constraint concerning the types of variables to be accessed in the parallel programs, such that a high system extensibility can be realized. The system is formed by a plurality of processor units coupled through a shared bus, where each processor unit comprises: a CPU; a main memory connected with the CPU through an internal bus, for storing a distributed part of data entries of a shared-memory of the system; a cache memory associated with the CPU and connected with the main memory through the internal bus, for caching selected data entries of the shared-memory; and a sharing management unit connected with the main memory and the cache memory through the internal bus, For interfacing the internal bus and the shared bus according to a sharing state for each data entry of the main memory and a cache state of each data entry of the cache memory.