Patents by Inventor Takashi Orimoto
Takashi Orimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230418011Abstract: A device includes a photonic integrated circuit (PIC) die and an electronic integrated circuit (EIC) die bonded to the PIC die. The PIC die includes a waveguide layer including a waveguide and a grating coupler configured to couple incident light into the waveguide, and a first set of dielectric layers on the waveguide layer. The EIC die includes a semiconductor substrate and a second set of dielectric layers on the semiconductor substrate. The first set of dielectric layers faces the second set of dielectric layers. The PIC die and the EIC die include a trench aligned with the grating coupler, the trench extending through the semiconductor substrate, the second set of dielectric layers, and the first set of dielectric layers to the waveguide layer such that the incident light may pass through the trench to reach the grating coupler. A multi-step dry etching process is used to form the trench.Type: ApplicationFiled: November 9, 2021Publication date: December 28, 2023Inventors: George A. KOVALL, Takashi ORIMOTO, Gabriel MENDOZA, Vimal KAMINENI, Himani KAMINENI, Luu NGUYEN
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Patent number: 10403639Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers over a substrate. An array of drain select level assemblies including cylindrical electrode portions is formed over the alternating stack with the same periodicity as the array of memory stack structures. A drain select level isolation strip including dielectric materials can be formed between a neighboring pair of drain select level assemblies employing the drain select level assemblies as a self-aligning template. Alternatively, cylindrical electrode portions can be formed around an upper portion of each memory stack structure. Strip electrode portions are formed on the cylindrical electrode portions after formation of the drain select level isolation strip.Type: GrantFiled: November 20, 2017Date of Patent: September 3, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Takashi Orimoto, James Kai, Sayako Nagamine, Takaaki Iwai, Shigeyuki Sugihara, Shuji Minagawa
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Patent number: 10297610Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers over a substrate. An array of drain select level assemblies including cylindrical electrode portions is formed over the alternating stack with the same periodicity as the array of memory stack structures. A drain select level isolation strip including dielectric materials can be formed between a neighboring pair of drain select level assemblies employing the drain select level assemblies as a self-aligning template. Alternatively, cylindrical electrode portions can be formed around an upper portion of each memory stack structure. Strip electrode portions are formed on the cylindrical electrode portions after formation of the drain select level isolation strip.Type: GrantFiled: November 20, 2017Date of Patent: May 21, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: James Kai, Johann Alsmeier, Shinsuke Yada, Akihisa Sai, Sayako Nagamine, Takashi Orimoto, Tong Zhang
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Publication number: 20190027488Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers over a substrate. An array of drain select level assemblies including cylindrical electrode portions is formed over the alternating stack with the same periodicity as the array of memory stack structures. A drain select level isolation strip including dielectric materials can be formed between a neighboring pair of drain select level assemblies employing the drain select level assemblies as a self-aligning template. Alternatively, cylindrical electrode portions can be formed around an upper portion of each memory stack structure. Strip electrode portions are formed on the cylindrical electrode portions after formation of the drain select level isolation strip.Type: ApplicationFiled: November 20, 2017Publication date: January 24, 2019Inventors: James KAI, Johann ALSMEIER, Shinsuke YADA, Akihisa SAI, Sayako NAGAMINE, Takashi ORIMOTO, Tong ZHANG
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Publication number: 20190027489Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers over a substrate. An array of drain select level assemblies including cylindrical electrode portions is formed over the alternating stack with the same periodicity as the array of memory stack structures. A drain select level isolation strip including dielectric materials can be formed between a neighboring pair of drain select level assemblies employing the drain select level assemblies as a self-aligning template. Alternatively, cylindrical electrode portions can be formed around an upper portion of each memory stack structure. Strip electrode portions are formed on the cylindrical electrode portions after formation of the drain select level isolation strip.Type: ApplicationFiled: November 20, 2017Publication date: January 24, 2019Inventors: Takashi ORIMOTO, James KAI, Sayako Najamine, Takaaki Iwai, Shigeyuki Sugihara, Shuji Minagawa
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Patent number: 10103169Abstract: At least one alternating stack of insulating layers and silicon nitride layers is formed over a substrate. Memory stack structures are formed through the at least one alternating stack. A trench and an etch mask spacer are formed such that the trench extends through the entirety of the alternating stack while the etch mask covers upper layers of the at least one alternating stack. Lower silicon nitride layers are removed employing a first hot phosphoric acid wet etch process. After removal of the etch mask spacer, upper silicon nitride layers are removed employing a second hot phosphoric acid wet etch process. Electrically conductive layers are formed in the lateral recesses formed by removal of the silicon nitride layers.Type: GrantFiled: August 21, 2017Date of Patent: October 16, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Chun Ge, Fei Zhou, Yanli Zhang, Raghuveer S. Makala, Takashi Orimoto
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Patent number: 9754836Abstract: Disclosed are packaging methods for the fabrication of analytical device packages and fabricated analytical device packages. The methods include providing a sensor wafer and mounting individual plates or a plate wafer on the sensor wafer. The sensor wafer includes sensor chips with aperture regions and is treated with selective depositions, either prior to or during the fabrication of the analytical device packages, to produce different surface characteristics at different portions of the aperture regions. Before dicing the sensor wafer, openings of the individual plates or the plate wafer are covered by a protective layer to protect surface characteristics at different portions of the aperture regions. A fabricated analytical device package includes a sensor chip with different surface characteristics, a plate, a packaging substrate and an optional cover.Type: GrantFiled: November 17, 2016Date of Patent: September 5, 2017Assignee: Pacific Biosciences of California, Inc.Inventors: Ravi Saxena, Elizabeth Logan, Takashi Orimoto
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Publication number: 20170140990Abstract: Disclosed are packaging methods for the fabrication of analytical device packages and fabricated analytical device packages. The methods include providing a sensor wafer and mounting individual plates or a plate wafer on the sensor wafer. The sensor wafer includes sensor chips with aperture regions and is treated with selective depositions, either prior to or during the fabrication of the analytical device packages, to produce different surface characteristics at different portions of the aperture regions. Before dicing the sensor wafer, openings of the individual plates or the plate wafer are covered by a protective layer to protect surface characteristics at different portions of the aperture regions. A fabricated analytical device package includes a sensor chip with different surface characteristics, a plate, a packaging substrate and an optional cover.Type: ApplicationFiled: November 17, 2016Publication date: May 18, 2017Inventors: Ravi Saxena, Elizabeth Logan, Takashi Orimoto
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Patent number: 8946022Abstract: Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.Type: GrantFiled: February 22, 2013Date of Patent: February 3, 2015Assignee: SanDisk Technologies Inc.Inventors: Vinod Robert Purayath, James K Kai, Masaaki Higashitani, Takashi Orimoto, George Matamis, Henry Chien
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Publication number: 20140061771Abstract: A memory cell system is provided forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming an intermediate layer over the charge trap layer, and forming a second insulator layer with the intermediate layer.Type: ApplicationFiled: November 11, 2013Publication date: March 6, 2014Applicants: Spansion, LLC., Advanced Micro Devices, Inc.Inventors: Meng Ding, Amol Ramesh Joshi, Lei Xue, Takashi Orimoto, Kuo-Tung Chang
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Patent number: 8587049Abstract: A memory cell system is provided forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming an intermediate layer over the charge trap layer, and forming a second insulator layer with the intermediate layer.Type: GrantFiled: July 17, 2006Date of Patent: November 19, 2013Assignees: Spansion, LLC, Advanced Micro Devices, Inc.Inventors: Meng Ding, Amol Ramesh Joshi, Lei Xue, Takashi Orimoto, Kuo-Tung Chang
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Patent number: 8546152Abstract: A method of fabricating non-volatile memory is provided for memory cells employing a charge storage element with multiple charge storage regions. A first charge storage layer is formed over a tunnel dielectric layer at both a memory array region and an endpoint region of a semiconductor substrate. The first charge storage layer is removed from the endpoint region to expose the tunnel dielectric region. A second charge storage layer is formed over the first charge storage layer at the memory array region and over the tunnel dielectric layer at the endpoint region. When etching the second charge storage layer to form the stem regions of the memory cells, the tunnel dielectric layer provides a detectable endpoint signal to indicate that etching for the second charge storage layer is complete.Type: GrantFiled: December 19, 2007Date of Patent: October 1, 2013Assignee: SanDisk Technologies Inc.Inventors: Takashi Orimoto, George Matamis, James Kai, Vinod Robert Purayath
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Patent number: 8383479Abstract: Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.Type: GrantFiled: July 20, 2010Date of Patent: February 26, 2013Assignee: SanDisk Technologies Inc.Inventors: Vinod Robert Purayath, James K. Kai, Masaaki Higashitani, Takashi Orimoto, George Matamis, Henry Chien
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Patent number: 8263465Abstract: Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the nanodots to attach to sites in the coupling layer. The coupling layer is then dissolved such as by rinsing or nitrogen blow drying, leaving the nanodots on the gate oxide layer. The nanodots react with the coupling layer and become negatively charged and arranged in a uniform monolayer, repelling a deposition of an additional monolayer of nanodots. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.Type: GrantFiled: April 5, 2010Date of Patent: September 11, 2012Assignee: SanDisk Technologies Inc.Inventors: Vinod Robert Purayath, George Matamis, Takashi Orimoto, James Kai, Tuan D. Pham
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Patent number: 8222091Abstract: A method of making a device includes providing a first device level containing first semiconductor rails separated by first insulating features, forming a sacrificial layer over the first device level, patterning the sacrificial layer and the first semiconductor rails in the first device level to form a plurality of second rails extending in a second direction, wherein the plurality of second rails extend at least partially into the first device level and are separated from each other by rail shaped openings which extend at least partially into the first device level, forming second insulating features between the plurality of second rails, removing the sacrificial layer, and forming second semiconductor rails between the second insulating features in a second device level over the first device level. The first semiconductor rails extend in a first direction. The second semiconductor rails extend in the second direction different from the first direction.Type: GrantFiled: December 2, 2011Date of Patent: July 17, 2012Assignee: SanDisk 3D LLCInventors: Vinod Robert Purayath, George Matamis, James Kai, Takashi Orimoto
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Patent number: 8207036Abstract: A method for fabricating a non-volatile storage element. The method comprises forming a layer of polysilicon floating gate material over a substrate and forming a layer of nitride at the surface of the polysilicon floating gate material. Floating gates are formed from the polysilicon floating gate material. Individual dielectric caps are formed from the nitride such that each individual nitride dielectric cap is self-aligned with one of the plurality of floating gates. An inter-gate dielectric layer is formed over the surface of the dielectric caps and the sides of the floating gates. Control gates are then formed with the inter-gate dielectric layer separating the control gates from the floating gates. The layer of nitride may be formed using SPA (slot plane antenna) nitridation. The layer of nitride may be formed prior to or after etching of the polysilicon floating gate material to form floating gates.Type: GrantFiled: September 30, 2008Date of Patent: June 26, 2012Assignee: SanDisk Technologies Inc.Inventors: Vinod Robert Purayath, George Matamis, Takashi Orimoto, Henry Chien, James K. Kai
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Patent number: 8193055Abstract: Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, metal salt ions are added to a core of a copolymer solution. A metal salt reduction causes the metal atoms to aggregate in the core, forming a metal nanodot. The copolymer solution is applied to a gate oxide on a substrate using spin coating or dip coating. Due to the copolymer configuration, the nanodots are held in a uniform 2D grid on the gate oxide. The polymers are selected to provide a desired nanodot size and spacing between nanodots. A polymer cure and removal process leaves the nanodots on the gate oxide. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.Type: GrantFiled: December 18, 2007Date of Patent: June 5, 2012Assignee: SanDisk Technologies Inc.Inventors: Vinod Robert Purayath, George Matamis, Takashi Orimoto, James Kai, Tuan D. Pham
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Publication number: 20120077318Abstract: A method of making a device includes providing a first device level containing first semiconductor rails separated by first insulating features, forming a sacrificial layer over the first device level, patterning the sacrificial layer and the first semiconductor rails in the first device level to form a plurality of second rails extending in a second direction, wherein the plurality of second rails extend at least partially into the first device level and are separated from each other by rail shaped openings which extend at least partially into the first device level, forming second insulating features between the plurality of second rails, removing the sacrificial layer, and forming second semiconductor rails between the second insulating features in a second device level over the first device level. The first semiconductor rails extend in a first direction. The second semiconductor rails extend in the second direction different from the first direction.Type: ApplicationFiled: December 2, 2011Publication date: March 29, 2012Inventors: Vinod Robert PURAYATH, George MATAMIS, James KAI, Takashi ORIMOTO
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Patent number: 8143661Abstract: A memory cell system is provided including a first insulator layer over a semiconductor substrate, a charge trap layer over the first insulator layer, and slot where the charge trap layer includes a second insulator layer having the characteristic of being grown.Type: GrantFiled: October 10, 2006Date of Patent: March 27, 2012Assignees: Spansion LLC, Advanced Micro Devices, Inc.Inventors: Shenqing Fang, Rinji Sugino, Jayendra Bhakta, Takashi Orimoto, Hiroyuki Nansei, Yukio Hayakawa, Takayuki Maruyama, Hidehiko Shiraiwa, Kuo-Tung Chang, Lei Xue, Meng Ding, Amol Ramesh Joshi, YouSeok Suh, Harpreet Sachar
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Patent number: 8143156Abstract: High density semiconductor devices and methods of fabricating the same are disclosed. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which may be smaller than the smallest lithographically resolvable element size of the process being used. A first set of spacers may be processed to provide planar and parallel sidewalls. A second set of spacers may be formed on planar and parallel sidewalls of the first set of spacers. The second set of spacers serve as a mask to form one or more circuit elements in a layer beneath the second set of spacers. The steps according to embodiments of the invention allow a recursive spacer technique to be used which results in robust, evenly spaced, spacers to be formed and used as masks for the circuit elements.Type: GrantFiled: June 20, 2007Date of Patent: March 27, 2012Assignee: SanDisk Technologies Inc.Inventors: George Matamis, James Kai, Takashi Orimoto, Nima Mokhlesi