Abstract: A semiconductor device has a peak value storage register, a threshold value storage register, a peak determination circuit, and an end timing determination circuit. The peak determination circuit determines whether or not to update a value stored in the peak value storage register. Further, the peak determination circuit ends an operation if the end timing determination circuit determines that an end timing has arrived. The peak value storage register updates a storage value if the peak determination circuit determines to perform updating. The end timing determination circuit determines that the end timing of the operation of the peak determination circuit has arrived if the value of an input signal becomes smaller than a value obtained by decreasing or increasing the value stored in the peak value storage register by a value corresponding to a threshold value stored in the threshold value storage register.

Abstract: A semiconductor device has a peak value storage register, a threshold value storage register, a peak determination circuit, and an end timing determination circuit. The peak determination circuit determines whether or not to update a value stored in the peak value storage register. Further, the peak determination circuit ends an operation if the end timing determination circuit determines that an end timing has arrived. The peak value storage register updates a storage value if the peak determination circuit determines to perform updating. The end timing determination circuit determines that the end timing of the operation of the peak determination circuit has arrived if the value of an input signal becomes smaller than a value obtained by decreasing or increasing the value stored in the peak value storage register by a value corresponding to a threshold value stored in the threshold value storage register.

Abstract: The present invention provides an interrupt generation circuit that can reduce the time between the moment a monitored object actually enters a desired state and the moment an interrupt is generated. An external event detection unit 101 detects the effective edge of an external event signal. A count period generation circuit 103 generates external event division signals which are counted by the main timer 104 and each of which has a period that is 1/N of the time interval between the effective edges of the immediately preceding external event signal. A compare register 105 stores a value corresponding to the time at which an interrupt is to be generated. When the count value of the main timer 104 becomes equal to or larger than the value stored in the compare register 105, the interrupt determination circuit 106 generated an interrupt.

Abstract: A method of making a bicycle wheel rim comprises the steps of forming a ring-shaped wheel rim body having a rotational axis, and dipping the rim body in a coloring agent to form a colored surface so that a first color difference portion and a second color difference portion are formed on opposite sides of the rim body.

Abstract: A bicycle wheel rim comprises a ring-shaped wheel rim body having a rotational axis. A colored surface is formed by dipping the rim body in a coloring agent so that a first color difference portion and a second color difference portion are formed on opposite sides of the rim body.

Abstract: The present invention provides an interrupt generation circuit that can reduce the time between the moment a monitored object actually enters a desired state and the moment an interrupt is generated. An external event detection unit 101 detects the effective edge of an external event signal. A count period generation circuit 103 generates external event division signals which are counted by the main timer 104 and each of which has a period that is 1/N of the time interval between the effective edges of the immediately preceding external event signal. A compare register 105 stores a value corresponding to the time at which an interrupt is to be generated. When the count value of the main timer 104 becomes equal to or larger than the value stored in the compare register 105, the interrupt determination circuit 106 generated an interrupt.

Abstract: A snowboard interface has an upper interface and a lower interface, wherein the upper interface rotates and translates relative to the lower interface.