Patents by Inventor Takashi Ozawa

Takashi Ozawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7884463
    Abstract: On a semiconductor element loading face, wiring patterns are drawn out from those formed in the vicinity of the edge of the semiconductor element of the loading pads formed to correspond to the electrode terminals of the semiconductor element, and connected to via pads formed in the vicinity of the edge of the semiconductor element loading face; area pads constructed of the loading pads corresponding to the electrode terminals formed in the central region of the semiconductor element and its vicinity are electrically connected to external connecting terminal pads formed in the central region on the other side of the wiring board and its vicinity, through the nearest area pad vias encircled by the external connecting terminal pads and passing through the wiring board and the wiring patterns; and a plurality of the loading pads constituting the area pads commonly use one of the area pad vias.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: February 8, 2011
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Takashi Ozawa, Hitoshi Sato
  • Patent number: 7884482
    Abstract: It is a flip-chip mounting substrate according to the invention has a wiring pattern in which bonding pads and predetermined parts of lead wires continuously extending from the bonding pads are exposed from an insulating layer or a solder resist. In the flip-chip mounting substrate, exposed parts of the wiring pattern are formed in to a plurality of different shapes. The exposed parts are formed so that the areas of the bonding pads are substantially equal to one another, and that the total areas of predetermined parts of the lead wires continuously extending from the bonding pads are substantially equal to one another.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: February 8, 2011
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Takashi Ozawa, Yasushi Araki, Masatoshi Nakamura, Seiji Sato
  • Patent number: 7869261
    Abstract: A semiconductor memory maintains securely the stored contents in the memory cells, and it is written with data reliably even in a case where a relatively low supply voltage is applied. A memory cell M00 comprises a pair of inverters cross-coupled with each other, a first switching unit provided between bit line BL and the output terminal of one of the inverters, and a second switching unit provided between bit line XBL and the output terminal of the other inverter. The first switching unit and the second switching unit are controlled to be conductive such that the conductance of the switches be larger for the writing operation than for the reading operation.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: January 11, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Takashi Ozawa
  • Patent number: 7847417
    Abstract: A solder resist and a central pad to which a central Au bump provided on a semiconductor chip is flip-chip bonded are formed on a substrate main body. In a flip-chip mounting substrate where an underfill resin is provided after the semiconductor chip is mounted, a central opening portion for exposing the central pad is formed in the solder resist, and also, an edge portion forming the central opening portion of the solder resist is partially overlapped with the outer peripheral portion of the central pad.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: December 7, 2010
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Yasushi Araki, Seiji Sato, Masatoshi Nakamura, Takashi Ozawa
  • Publication number: 20100295174
    Abstract: A wiring substrate includes: a semiconductor chip on which a plurality of bumps are mounted, and a plurality of connection pads which are joined to the bumps mounted on the semiconductor chip in a flip chip method, wherein the connection pads of a peripheral portion of the wiring substrate are formed in a non-solder mask defined structure, and the connection pads of a center portion of the wiring substrate are formed in a solder mask defined structure.
    Type: Application
    Filed: May 18, 2010
    Publication date: November 25, 2010
    Applicant: Shinko Electric Industries Co., Ltd.
    Inventors: Takashi Ozawa, Seiji Sato
  • Patent number: 7838998
    Abstract: A mounting substrate for mounting a semiconductor chip in a flip chip manner, having a plurality of connection pads to which the semiconductor chip is connected, an insulating pattern formed so as to cover a part of the connection pads, and a plurality of dummy patterns for controlling a flow of an underfill infiltrated below the semiconductor chip, characterized in that the plurality of dummy patterns are arranged in staggered lattice shape.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: November 23, 2010
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Takashi Ozawa, Yasushi Araki, Masatoshi Nakamura, Seiji Sato
  • Patent number: 7835616
    Abstract: An information presentation system for supporting interactions based on presentation of various pieces of information in a scene where persons face each other, the information presentation system includes: a plurality of display record media, each having a unique identifier, where display information can be rewritten; an information selection section that selects information to be displayed on the display record medium; an information rewrite section that is detachably attached to the display record medium, and that rewritably writes the information selected by the information selection section to the display record medium in a state where the display record medium is attached to the information rewrite section; a history storage section that records a history of the information in association with the unique identifier of the display record medium; and a manipulation detection section that detects a selective manipulation of a user on the display record medium.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: November 16, 2010
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Minoru Koshimizu, Naoki Hayashi, Hiroyuki Hotta, Shigehiko Sasaki, Yoshitsugu Hirose, Tsutomu Ishii, Masahiro Sato, Takashi Ozawa
  • Publication number: 20100252938
    Abstract: A semiconductor package includes: a semiconductor element mounted on a one-sided plane of a wiring board; an underfill agent dropped so as to be filled between the semiconductor element and the wiring board; and a pad group constituted by a plurality of pads which are formed in the vicinity of a circumference of the wiring board and along the circumference, the pad group being formed on a bottom plane of a groove portion formed in a solder resist which covers the one-sided plane of the wiring board, wherein a corner edge of the groove portion located in the vicinity of a dropping starting portion to which dropping of the underfill agent is started is formed at an obtuse angle or in an arc shape in order to avoid the dropped underfill agent from entering into an inner portion of the groove portion.
    Type: Application
    Filed: March 31, 2010
    Publication date: October 7, 2010
    Applicant: Shinko Electric Industries Co., Ltd.
    Inventors: Takashi OZAWA, Seiji Sato, Kazuyuki Izumi
  • Patent number: 7776144
    Abstract: To provide inks and ink sets for inkjet recording, which have good fastness and good jet-out stability and which give good images with no bleeding trouble, yellow ink, black ink and magenta ink for inkjet printing contain at least two dyes each having an oxidation potential over 1.0 V (vs SCE).
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: August 17, 2010
    Assignee: FUJIFILM Corporation
    Inventors: Toshiki Taguchi, Takashi Ozawa, Manabu Ogawa, Naotaka Wachi
  • Publication number: 20100165302
    Abstract: A projector adapted to perform a keystone distortion correction for correcting keystone distortion of an image projected on a projection surface, includes: a fluctuation detection section adapted to start detection of fluctuation state of the projector in response to a predetermined instruction signal; an angle detection section adapted to detect an installation angle of the projector; a distortion correction section adapted to perform the keystone distortion correction, in response to detection of a fluctuation settled state by the fluctuation detection section, in accordance with the installation angle detected by the angle detection section; and a control section adapted to terminate the detection of the fluctuation state by the fluctuation detection section in response to elapse of second time while keeping the fluctuation settled state from completion of the keystone distortion correction by the distortion correction section.
    Type: Application
    Filed: December 7, 2009
    Publication date: July 1, 2010
    Applicant: Seiko Epson Corporation
    Inventor: Takashi Ozawa
  • Publication number: 20100134764
    Abstract: A projector includes: a light source; a light modulation device which forms an image by modulating light emitted from the light source according to inputted image information; a projection optical system which projects the image formed by the light modulation device; a projection position controlling unit which controls the projection position of the image by shifting the projection optical system in the left-right direction with respect to the projection direction; a pair of left and right speakers which output sounds corresponding to audio information inputted with the image information; and a sound volume adjusting unit which separately adjusts sound volume levels of the sounds outputted from the pair of the speakers based on the control condition of the projection position provided by the projection position controlling unit.
    Type: Application
    Filed: July 9, 2009
    Publication date: June 3, 2010
    Applicant: Seiko Epson Corporation
    Inventor: Takashi Ozawa
  • Publication number: 20100127370
    Abstract: On a semiconductor element loading face, wiring patterns are drawn out from those formed in the vicinity of the edge of the semiconductor element of the loading pads formed to correspond to the electrode terminals of the semiconductor element, and connected to via pads formed in the vicinity of the edge of the semiconductor element loading face; area pads constructed of the loading pads corresponding to the electrode terminals formed in the central region of the semiconductor element and its vicinity are electrically connected to external connecting terminal pads formed in the central region on the other side of the wiring board and its vicinity, through the nearest area pad vias encircled by the external connecting terminal pads and passing through the wiring board and the wiring patterns; and a plurality of the loading pads constituting the area pads commonly use one of the area pad vias.
    Type: Application
    Filed: November 25, 2009
    Publication date: May 27, 2010
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Takashi Ozawa, Hitoshi Sato
  • Publication number: 20100123545
    Abstract: A projection system includes: a screen having screen specific authentication information; and a projector having a function of acquiring the screen specific authentication information and, based on the acquired authentication information, carrying out an authentication process for setting the projector to a usable condition.
    Type: Application
    Filed: October 28, 2009
    Publication date: May 20, 2010
    Applicant: Seiko Epson Corporation
    Inventor: Takashi Ozawa
  • Patent number: 7660835
    Abstract: An information processing system for management of various pieces of information, the information processing system includes: a plurality of display record media, each having a unique identifier; an information selection section that selects information to be displayed; an information rewrite section that rewritably writes the information; a manipulation detection section that detects a selective manipulation of a user on the display record medium; a history storage section that records a history of the information and a history of the manipulations in association with a unique identifier of the display record medium, respectively; a manipulation history determination section for a user to determine any manipulation history out of a list of the histories of the manipulations; and an information search section that searches for at least one of a history of the information, a history of other manipulations and a unique identifier of the display record medium.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: February 9, 2010
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Naoki Hayashi, Hiroyuki Hotta, Minoru Koshimizu, Yoshitsugu Hirose, Tsutomu Ishii, Shigehiko Sasaki, Masahiro Sato, Takashi Ozawa
  • Publication number: 20090283317
    Abstract: A wiring board between which and a chip to be mounted a resin is filled includes: a substrate body on which a conductor portion to be connected to an electrode terminal of the chip is formed; and an insulating protection film formed on the substrate body and having an opening portion formed therein to expose the conductor portion. The opening portion is formed in such a manner that the edge thereof is positioned along and outside the outer shape of the chip except for a specific corner portion, and that the edge in the specific corner portion is positioned on a side of or inside the outer shape of the chip.
    Type: Application
    Filed: May 14, 2009
    Publication date: November 19, 2009
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Takashi OZAWA
  • Publication number: 20090250812
    Abstract: A solder resist and a central pad to which a central Au bump provided on a semiconductor chip is flip-chip bonded are formed on a substrate main body. In a flip-chip mounting substrate where an underfill resin is provided after the semiconductor chip is mounted, a central opening portion for exposing the central pad is formed in the solder resist, and also, an edge portion forming the central opening portion of the solder resist is partially overlapped with the outer peripheral portion of the central pad.
    Type: Application
    Filed: June 4, 2009
    Publication date: October 8, 2009
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Yasushi Araki, Seiji Sato, Masatoshi Nakamura, Takashi Ozawa
  • Patent number: 7533978
    Abstract: A coloring composition containing a dis-azo compound or poly-azo compound which contains two or more substituents having a pKa value in water of ?i0 to 5 and which has an oxidation potential more positive than 0.8 V (vs SCE), and an inkjet recording ink composition containing the coloring composition and an inkjet recording method wherein an image is formed on an image-receiving material containing a support having provided thereon an ink receiving layer containing a white inorganic pigment particle, using the inkjet recording ink composition.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: May 19, 2009
    Assignee: Fujifilm Corporation
    Inventors: Tomohiro Chino, Toshiki Fujiwara, Takashi Ozawa, Yoshiharu Yabuki
  • Publication number: 20090102062
    Abstract: A wiring substrate of the present invention includes such a structure that a plurality of connection pads and leading wiring portions connected to the plurality of connection pads respectively are arranged to an insulating layer of a surface layer side, and the leading wiring portions are arranged to be bended from the connection pads, and a solder layer to protrude upward is provided on the connection pads respectively. A solder on the leading wiring portions moves to the bend portion side, and thus the solder layer to protrude upward is formed on the connection pads.
    Type: Application
    Filed: October 20, 2008
    Publication date: April 23, 2009
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Seiji Sato, Takashi Ozawa
  • Patent number: 7510605
    Abstract: To provide a dye which has a good hue, which can form an image showing a high fastness under various using conditions and environmental conditions, and which is particularly suited for an ink, the dye is represents by formula (1): wherein R1 and R2 each independently represents a monovalent group, Z represents a nitrogen atom or a carbon atom to which a hydrogen atom or a monovalent group is bonded, and M represents a hydrogen atom or a cation, provided that the dye has two azo groups.
    Type: Grant
    Filed: February 3, 2005
    Date of Patent: March 31, 2009
    Assignee: Fujifilm Corporation
    Inventors: Toru Harada, Yoshiharu Yabuki, Takashi Ozawa, Keiichi Tateishi
  • Patent number: 7507282
    Abstract: A novel ink composition, which has an absorption characteristic excellent in color reproducibility as a yellow color of one of the three primary colors, which has enough fastness against light, heat and humidity, and which does not cause bronze phenomenon, is provided. The ink composition contains water, a yellow dye having an oxidation potential nobler than 1.0 V, and an aromatic compound, aliphatic compound and/or a salt thereof having at least one of carboxyl group, sulfo group and phosphoric acid group.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: March 24, 2009
    Assignee: FUJIFILM Corporation
    Inventors: Takashi Ozawa, Keiichi Tateishi, Toru Harada