Patents by Inventor Takashi Saka

Takashi Saka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140240873
    Abstract: A switching power supply circuit includes a transformer having primary, secondary and tertiary windings; a primary-side rectifying-and-smoothing circuit that converts AC power to DC power then smoothes it; a secondary-side rectifying-and-smoothing circuit that smoothes secondary-side power; a tertiary-side rectifying-and-smoothing circuit that smoothes power from the tertiary winding; a switching circuit that switches the primary winding; a pulse width control circuit that controls the switching of the switching circuit; an output-error detecting circuit that detects a deviation of a secondary-side DC output voltage from a reference voltage; and a ripple-voltage detecting-and-controlling circuit that detects a ripple-voltage of the secondary-side DC output voltage and stop-controls the output-error detecting circuit, wherein a stop-control signal from the ripple-voltage detecting-and-controlling circuit causes the output-error detecting circuit to stop outputting, then a drive signal to the switching circuit
    Type: Application
    Filed: August 28, 2012
    Publication date: August 28, 2014
    Applicant: I-O DATA DEVICE, INC.
    Inventor: Takashi Saka
  • Publication number: 20130170621
    Abstract: The present invention includes: a transformer having a primary winding, a secondary winding and a tertiary winding; a primary-side rectifying and smoothing circuit, which converts alternating-current power to direct-current power and smoothes the power; a secondary-side rectifying and smoothing circuit, which smoothes secondary-side power; a tertiary-side rectifying and smoothing circuit, which smoothes power of the tertiary winding; a switching circuit, which opens and closes the primary winding; a pulse width control circuit, which controls the pulse width of drive signals that control the opening and closing of the switching circuit; and a secondary-side electrolytic capacitor deterioration detecting circuit, which detects deterioration of the secondary-side electrolytic capacitor.
    Type: Application
    Filed: September 2, 2011
    Publication date: July 4, 2013
    Applicant: I-O DATA DEVICE INC
    Inventors: Takashi Saka, Shigeta Akiyama, Kazuhiro Matsuda, Katsuichiro Otsuka
  • Patent number: 8344354
    Abstract: A spin-polarized electron generating device includes a substrate, a buffer layer, a strained superlattice layer formed on the buffer layer, and an intermediate layer formed of a crystal having a lattice constant greater than a lattice constant of a crystal of the buffer layer, the intermediate layer intervening between the substrate and the buffer layer. The buffer layer includes cracks formed in a direction perpendicular to the substrate by tensile strain.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: January 1, 2013
    Assignee: National University Corporation Nagoya University
    Inventors: Toru Ujihara, Xiuguang Jin, Yoshikazu Takeda, Tsutomu Nakanishi, Naoto Yamamoto, Takashi Saka, Toshihiro Kato
  • Publication number: 20110089397
    Abstract: To provide implement a spin-polarized electron generating device having high spin polarization and high external quantum efficiency while allowing a certain degree of freedom in selecting materials of a substrate, a buffer layer, and a strained superlattice layer. In a spin-polarized electron generating device having a substrate, a buffer layer, and a strained superlattice layer formed on the buffer layer, an intermediate layer formed of a crystal having a lattice constant greater than that of a crystal used to form the buffer layer intervenes between the substrate and the buffer layer. With this arrangement, tensile strain causes cracks to be formed in the buffer layer in a direction perpendicular to the substrate, whereby the buffer layer has mosaic-like appearance. As a result, glide dislocations in an oblique direction do not propagate to the strained superlattice layer to be grown on the buffer layer, thereby improving crystallinity of the strained superlattice layer.
    Type: Application
    Filed: March 24, 2009
    Publication date: April 21, 2011
    Inventors: Toru Ujihara, Xiuguang Jin, Yoshikazu Takeda, Tsutomu Nakanishi, Naoto Yamamoto, Takashi Saka, Toshihiro Kato
  • Patent number: 5834791
    Abstract: A process of producing a highly spin-polarized electron beam, including the steps of applying a light energy to a semiconductor device comprising a first compound semiconductor layer having a first lattice constant and a second compound semiconductor layer having a second lattice constant different from the first lattice constant, the second semiconductor layer being in junction contact with the first semiconductor layer to provide a strained semiconductor heterostructure, a magnitude of mismatch between the first and second lattice constants defining an energy splitting between a heavy hole band and a light hole band in the second semiconductor layer, such that the energy splitting is greater than a thermal noise energy in the second semiconductor layer in use; and extracting the highly spin-polarized electron beam from the second semiconductor layer upon receiving the light energy.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: November 10, 1998
    Assignee: Daido Tokushuko Kabushiki Kaisha
    Inventors: Tsutomu Nakanishi, Hiromichi Horinaka, Takashi Saka, Toshihiro Kato
  • Patent number: 5723871
    Abstract: A process of producing a highly spin-polarized electron beam, including the steps of applying a light energy to a semiconductor device comprising a first compound semiconductor layer having a first lattice constant and a second compound semiconductor layer having a second lattice constant different from the first lattice constant, the second semiconductor layer being in junction contact with the first semiconductor layer to provide a strained semiconductor heterostructure, a magnitude of mismatch between the first and second lattice constants defining an energy splitting between a heavy hole band and a light hole band in the second semiconductor layer, such that the energy splitting is greater than a thermal noise energy in the second semiconductor layer in use; and extracting the highly spin-polarized electron beam from the second semiconductor layer upon receiving the light energy.
    Type: Grant
    Filed: March 17, 1994
    Date of Patent: March 3, 1998
    Assignee: Daido Tokushuko Kabushiki Kaisha
    Inventors: Tsutomu Nakanishi, Hiromichi Horinaka, Takashi Saka, Toshihiro Kato
  • Patent number: 5523572
    Abstract: A process of producing a highly spin-polarized electron beam, including the steps of applying a light energy to a semiconductor device comprising a first compound semiconductor layer having a first lattice constant and a second compound semiconductor layer having a second lattice constant different from the first lattice constant, the second semiconductor layer being in junction contact with the first semiconductor layer to provide a strained semiconductor heterostructure, a magnitude of mismatch between the first and second lattice constants defining an energy splitting between a heavy hole band and a light hole band in the second semiconductor layer, such that the energy splitting is greater than a thermal noise energy in the second semiconductor layer in use; and extracting the highly spin-polarized electron beam from the second semiconductor layer upon receiving the light energy.
    Type: Grant
    Filed: March 27, 1995
    Date of Patent: June 4, 1996
    Assignee: Daido Tokushuko Kabushiki Kaisha
    Inventors: Tsutomu Nakanishi, Hiromichi Horinaka, Takashi Saka, Toshihiro Kato
  • Patent number: 5315127
    Abstract: A semiconductor device for emitting, upon receiving a light energy, a highly spin-polarized electron beam, including a first compound semiconductor layer formed of gallium arsenide phosphide, GaAs.sub.l-x P.sub.x, and having a first lattice constant; a second compound semiconductor layer grown with gallium arsenide, GaAs, on the first compound semiconductor layer, and having a second lattice constant different from the first lattice constant, the second compound semiconductor layer emitting the highly spin-polarized electron beam upon receiving the light energy; and a fraction, x, of the gallium arsenide phosphide GaAs.sub.l-x P.sub.x and a thickness, t, of the second compound semiconductor layer defining a magnitude of mismatch between the first and second lattice constants, such that the magnitude of mismatch provides a residual strain, .epsilon..sub.R, of not less than 2.0.times.10.sup.-3 in the second layer. The fraction x of the gallium arsenide phosphide GaAs.sub.l-x P.sub.
    Type: Grant
    Filed: April 30, 1992
    Date of Patent: May 24, 1994
    Assignee: Daido Tokushuko Kabushiki Kaisha
    Inventors: Tsutmu Nakanishi, Hiromichi Horinaka, Takashi Saka, Toshihiro Kato
  • Patent number: 5260589
    Abstract: A semiconductor device having a reflecting layer consisting of unit semiconductors each consisting of two or more semiconductor films of different compositions. The thickness of the unit semiconductors varies continuously or in steps in the direction of thickness of the reflecting layer, preferably decreases in the direction toward the light incidence surface of the layer. For example, the reflecting layer has a varying-thickness portion whose unit semiconductors have a continuously varying thickness, and may include an iso-thickness portion whose semiconductors have the same thickness. The composition at the interface of the adjacent films preferably changes to mitigate a lattice mismatch which causes crystal defects of the layer.
    Type: Grant
    Filed: October 31, 1991
    Date of Patent: November 9, 1993
    Assignees: Norikatsu Yamauchi, Daido Tokushuko Kabushiki Kaisha
    Inventors: Norikatsu Yamauchi, Takashi Saka, Masumi Hirotani, Toshihiro Kato, Hiromoto Susawa
  • Patent number: 5132750
    Abstract: A light-emitting diode having a light-generating layer for generating an electromagnetic radiation by electroluminescence, a light-emitting surface through which the radiation is emitted, and a light-reflecting layer remote from the light-emitting surface, for reflecting a portion of the radiation toward the light-generating layer so that the radiation reflected by the light-reflecting layer is also emitted through the light-emitting surface. The light-reflecting layer consists of two or more interference type reflecting layers which include one or more reflecting layers each capable of most efficiently reflecting a wave whose wavelength is longer than the nominal wavelength of the radiation. The light-emitting surface may have irregularity for irregularly reflecting the radiation, or an anti-reflection layer formed thereon by deposition.
    Type: Grant
    Filed: November 20, 1990
    Date of Patent: July 21, 1992
    Assignee: Daido Tokushuko Kabushiki Kaisha
    Inventors: Toshihiro Kato, Hiromoto Susawa, Takashi Saka