Abstract: A transmitting apparatus for an interactive communication system using a broadcast wave is provided. The transmitting apparatus comprises a first storing unit for storing a plurality of frames of image data, a second storing unit for storing control information, for each frame of image data, showing a link to another frame of image data stored in the first storing unit, and a transmitting unit for repeatedly transmitting a predetermined number of frames of image data together with corresponding control information.

Abstract: An instruction fetching device includes one or both of a cache device and a branch history table. The cache device stores a plurality of pairs, each pair including an instruction string divided into minimum unit instructions and an address of the instruction string. At the time of reading an instruction, an instruction string is selected and output by every minimum unit instruction from at least two pairs. The branch history table stores a plurality of pairs, each pair including a branch destination address and a set of an address of a branch instruction and a value obtained by subtracting a given value from the address.

Abstract: This data processor makes zero the execution clock count of a branch instruction, a compare instruction, or a compare instruction and following branch instruction when a series of instructions executed in the past is again executed. The data processor of this invention is provided with a history storage unit which stores as its address tag the address of an instruction executed before the branch instruction or compare instruction, and stores the address of an instruction to be executed next the branch or compare instruction or both instruction code of an instruction to be executed next the branch or compare instruction and an address used for pre-fetching an instruction following the instruction code. While the instruction before the branch or compare instruction is decoded, the history storage unit is searched to obtain an instruction to be next executed. The obtained instruction is executed immediately after the execution of the instruction immediately before the branch or compare instruction.

Abstract: A data processing apparatus for decoding and executing instructions in a parallel manner in a variable word length instruction format. A plurality of decoders is used in which while the primary instruction decoder is decoding an instruction, the probability of parallel decoding of the next instruction is detected, so that the primary instruction decoder and a secondary instruction decoder decode a variable word length instruction and a fixed word length instruction, respectively, in a parallel manner. A conditional branch instruction of a fixed word length and the subsequent instruction of a variable word length are decoded and executed in a parallel manner to increase the speed at which the conditional branch instruction is executed.