Abstract: A semiconductor device is provided in which, as a result of the number of tap cells being suppressed while the laying out of signal interconnects is made easier, the total layout area can be reduced.

Abstract: The manufacturing method of a semiconductor device can improve the mechanical strength of a pad more than before, and suppress the occurrence of a crack. The manufacturing method of a semiconductor device includes: forming a first pad constituted by a first metal layer; forming an insulating layer on the first pad; providing an opening portion in the insulating layer by removing the insulating layer on at least a partial region of the first pad; forming a second pad constituted by a second metal layer in the opening portion of the insulating layer so as to have a film thickness that is smaller than the film thickness of the insulating layer; and forming a third pad constituted by a third metal layer on the second pad.

Abstract: A scroll compressor is provided that can cool a fixed scroll and an orbiting scroll effectively via cooling fins. A scroll compressor includes: a fixed scroll, an orbiting scroll that performs orbiting motion with respect to the fixed scroll and is combined with the fixed scroll so as to form, with the fixed scroll, a compression space to compress fluid; cooling fins that are provided on the back of the fixed scroll; and cooling fins that are provided on the back of the orbiting scroll. The cooling fins and the cooling fins are taller in a central portion than in the circumference of the central portion.

Abstract: A semiconductor device is provided in which, as a result of the number of tap cells being suppressed while the laying out of signal interconnects is made easier, the total layout area can be reduced.

Abstract: The manufacturing method of a semiconductor device can improve the mechanical strength of a pad more than before, and suppress the occurrence of a crack. The manufacturing method of a semiconductor device includes: forming a first pad constituted by a first metal layer; forming an insulating layer on the first pad; providing an opening portion in the insulating layer by removing the insulating layer on at least a partial region of the first pad; forming a second pad constituted by a second metal layer in the opening portion of the insulating layer so as to have a film thickness that is smaller than the film thickness of the insulating layer; and forming a third pad constituted by a third metal layer on the second pad.

Abstract: A scroll compressor is provided that can cool a fixed scroll and an orbiting scroll effectively via cooling fins. A scroll compressor includes: a fixed scroll, an orbiting scroll that performs orbiting motion with respect to the fixed scroll and is combined with the fixed scroll so as to form, with the fixed scroll, a compression space to compress fluid; cooling fins that are provided on the back of the fixed scroll; and cooling fins that are provided on the back of the orbiting scroll. The cooling fins and the cooling fins are taller in a central portion than in the circumference of the central portion.

Abstract: A method for designing a layout of a semiconductor integrated circuit device includes placing a plurality of standard cells respectively constituting a plurality of functional blocks in a part of a logic circuit placement region, placing a plurality of basic cells in a part of regions of the logic circuit placement region in which no standard cells are placed, and placing at least one diode cell in at least a part of regions of the logic circuit placement region in which no standard cells and no basic cells are placed, the diode cell including a first and a second diode, the first diode being connected between a gate electrode of a predetermined transistor and a first power supply line and the second diode between the gate electrode and a second power supply line.

Abstract: A method for designing a layout of a semiconductor integrated circuit device includes placing a plurality of standard cells respectively constituting a plurality of functional blocks in a part of a logic circuit placement region, placing a plurality of basic cells in a part of regions of the logic circuit placement region in which no standard cells are placed, and placing at least one diode cell in at least a part of regions of the logic circuit placement region in which no standard cells and no basic cells are placed, the diode cell including a first and a second diode, the first diode being connected between a gate electrode of a predetermined transistor and a first power supply line and the second diode between the gate electrode and a second power supply line.

Abstract: An output current varying circuit 10 includes a control signal generating circuit 12, an output current supplying circuit 14 and an output terminal 16. Circuit 12 receives an output signal Sout of a dedicated logic circuit 11, and an output signal S1 from a predetermined circuit or an external signal S2 from an input terminal 13, and generates first and second control signals C1 and C2. Circuit 14 is constituted by two P-channel MIS transistors Tr1 and Tr2 connected in parallel between high potential Vdd and output terminal 16. When output signal Sout from logic circuit 11 is at H level, transistor Tr2 is in an on state and an output current i at H level appears on output terminal 16. When output signal Sout is a L level and a current value changing signal S is at L level, transistors Tr1 and Tr2 are both in an off state and the output current is zero.

Abstract: In a master slice integrated circuit device composed of an array of internal cells having contact members, an array of external cells having contact members and formed outwardly from the internal cell array, a main power circuit region formed on the external cell array, a plurality of power lines formed on the internal array region, and a plurality of signal lines for electrically interconnecting selected contact members of the internal and external cells, intermediate power line connection regions are provided to conductively connect each power line to the main power circuit region, the intermediate connection regions including, for each power line, a power branch-off member disposed at a given position on the main power circuit region and extending substantially in the direction of its respective power line, and a connection allowance member intersecting, and connected to, the power branch-off member and having a predetermined length, the connection allowance member being conductively connected between its

Abstract: Disclosed is a semiconductor device having complementary metal insulator semiconductor field-effect transistors (MISFETs) in which a plurality of basic cells having N-channel MOSs and P-channel MOSs are disposed. In this semiconductor device, a sub MISFET is disposed adjacently to a stopper layer in a region adjacent to other basic cell. An element such as a transmission gate composed of a single element can be actualized by use of the sub-MISFET. In the semiconductor device of this invention, a working efficiency thereof is improved. A response velocity of the P-channel MOS can also be improved using the sub-MISFET. A numerical quantity of the basic cells constituting a circuit can be reduced, resulting in a reduction in parasitic capacity. An operating time of the circuit is thereby decreased.

Abstract: In a master slice integrated circuit device composed of an array of internal cells having contact members, an array of external cells having contact members and formed outwardly from the internal cell array, a main power circuit region formed on the external cell array, a plurality of power lines formed on the internal array region, and a plurality of signal lines for electrically interconnecting selected contact members of the internal and external cells, intermediate power line connection regions are provided to conductively connect each power line to the main power circuit region, the intermediate connection regions including, for each power line, a power branch-off member disposed at a given position on the main power circuit region and extending substantially in the direction of its respective power line, and a connection allowance member intersecting, and connected to, the power branch-off member and having a predetermined length, the connection allowance member being conductively connected between its

Abstract: A semiconductor device assembly composed of a plurality of unit semiconductor devices formed into a logic circuit by selective connection among elements in the unit devices and among the unit devices. Each of the unit devices includes at least a first insulated-gate type field-effect transistor of a first conductivity type and a second insulated-gate type field-effect transistor of a second conductivity type which is disposed adjacent to the first transistor and has a gate electrode separated from a gate electrode of the first transistor. The gate electrodes of the respective transistors have at least a gate terminal portion at the side adjacent to each other, and the gate terminal portion of the first field-effect transistor has at least a first wire connecting location and a second wire connecting location. By using the second wire connecting location, wiring in and among the unit devices can be carried out via the shortest aluminum wires of a first layer, so that the wiring feasibility can be enhanced.