Abstract: A driver circuit includes a main driver which receives an input signal and outputs a first signal corresponding to the input signal, a sub driver which receives the input signal and outputs a non-inverted signal and an inverted signal corresponding to the input signal, a differentiating circuit including resistors and a variable capacity condenser, which outputs signals by differentiating the non-inverted signal and the inverted signal, respectively, and an addition unit which outputs a high frequency emphasized signal given by adding the output signal of the main driver and the signal given by differentiating the non-inverted signal, or a low frequency emphasized signal given by adding the output signal of the main driver and the signal given by differentiating the inverted signal.

Abstract: In a driver circuit 10 for outputting a simulated signal simulating an input signal subjected to transmission loss, corresponding to the input signal, the driver circuit 10 comprises: a main driver 18 which receives the input signal and outputs an output signal corresponding to the input signal; a sub driver 20 which receives the input signal and outputs an output signal given by inverting the input signal; a high frequency emphasizing circuit 22 which receives the input signal of the sub driver 20 and outputs an output signal having the high frequency of the input signal of the sub driver 20 emphasized; and an addition unit 24 which outputs the simulated signal given by adding the output signal of the main driver 18 and the output signal of the high frequency emphasizing circuit 22.

Abstract: Provided is a driver circuit that outputs a transmission signal according to a reception signal received from outside, including a first driver that outputs a voltage according to an input first signal; a second driver that receives the voltage output by the first driver as a power supply voltage and outputs the transmission signal according to the power supply voltage and an input second signal; and a control section that delays both the first signal and the second signal, according to a change of the reception signal, and causes the transmission signal according to the reception signal to be output from the second driver.

Abstract: A transmission line driving circuit that can support a high-rate signal transmission and further can perform appropriate loss compensation in accordance with a signal pattern. A transmission line driving circuit 1 comprises a plurality of driver input circuits 20 that serve as signal analyzing unit for analyzing the content of the signal pattern of an input signal; a plurality of lowpass filters 30; a plurality of gain adjusting circuits 40; a plurality of adders 50; and adder 52; and a driver output circuit 60 that outputs, in accordance with a signal analysis result, a signal the phase of which has been adjusted in such a direction that cancels the timing deviation caused by a loss occurring when the input signal is transmitted to the transmission path. The output signal from the driver output circuit 60 is transmitted to the transmission path 2.

Abstract: Provided is a test apparatus for testing a device under test, the test apparatus including: a pattern generating section that inputs a test pattern to the device under test; a judging section that receives an output signal of the device under test, and makes judgment concerning pass/fail of the device under test based on the output signal; an internal circuit that exchanges signals between the device under test and the pattern generating section or the judging section; a first transmission line that connects the internal circuit to the device under test; and a first switch that connects the first transmission line to a ground potential in not testing the device under test, and cuts off the first transmission line from the ground potential in testing of the device under test.

Abstract: A jitter generating circuit wherein a simple structure can be used to generate a pattern effect jitter. A jitter generating circuit 1 comprises a driver input circuit 20 that serves as a signal analyzing unit for analyzing the contents of the signal pattern of an input signal; a plurality of gain adjusting circuits 30; a plurality of lowpass filters 40; a plurality of adders 50; an adder 52; and a driver output circuit 60 that outputs a signal obtained by adjusting, in accordance with a signal analysis result, the phase of the input signal in such a direction in which the change timing deviates when the input signal is transmitted to the transmission line. Thus, the phase of an input signal is adjusted, thereby adding the jitter to the input signal.

Abstract: There is provided a signal transfer system that has a driver for outputting a signal, a transmission line for transmitting the signal, an insertion-type attenuator, inserted into the transmission line in series, for largely attenuating the low-frequency signal more than a high-frequency signal and an additional-type attenuator, inserted between the transmission line and a reference potential, for largely attenuating the low-frequency signal more than the high-frequency signal, and that matches composite impedance generated by the driver, the insertion-type attenuator and the additional-type attenuator with impedance of the transmission line.

Abstract: A jitter generating circuit wherein a simple structure can be used to generate a pattern effect jitter. A jitter generating circuit 1 comprises a driver input circuit 20 that serves as a signal analyzing unit for analyzing the contents of the signal pattern of an input signal; a plurality of gain adjusting circuits 30; a plurality of lowpass filters 40; a plurality of adders 50; an adder 52; and a driver output circuit 60 that outputs a signal obtained by adjusting, in accordance with a signal analysis result, the phase of the input signal in such a direction in which the change timing deviates when the input signal is transmitted to the transmission line. Thus, the phase of an input signal is adjusted, thereby adding the jitter to the input signal.

Abstract: Provided is a driver circuit that has a first operational mode and a second operational mode and outputs an output signal according to an input signal. The driver circuit includes a first driver section that, in the first operational mode, generates and outputs the output signal according to the input signal and, in the second operational mode, is controlled to be disabled; a high precision driver section that, in the first operational mode, is controlled to be disabled and, in the second operational mode, outputs a source power having a predetermined voltage; and a second driver section that, in the first operational mode, receives the output signal output by the first driver section and outputs the received signal to the outside and, in the second operational mode, receives the source power from the high precision driver section, generates the output signal according to the input signal, and outputs the thus generated signal to the outside.

Abstract: In a driver circuit 10 for outputting a simulated signal simulating an input signal subjected to transmission loss, corresponding to the input signal, the driver circuit 10 comprises: a main driver 18 which receives the input signal and outputs an output signal corresponding to the input signal; a sub driver 20 which receives the input signal and outputs an output signal given by inverting the input signal; a high frequency emphasizing circuit 22 which receives the input signal of the sub driver 20 and outputs an output signal having the high frequency of the input signal of the sub driver 20 emphasized; and an addition unit 24 which outputs the simulated signal given by adding the output signal of the main driver 18 and the output signal of the high frequency emphasizing circuit 22.

Abstract: The apparatus includes a first variable delay circuit that delays a data signal from a device under test (DUT) to output a delay data signal; a second variable delay circuit that delays a clock signal to output a first delay clock signal; a first FF that acquires the delay data signal based on a reference clock; a second FF that acquires the first delay clock signal based on the clock; a first delay adjusting section that adjusts a delay amount of at least one of the first and second variable delay circuits so that the first and second FFs acquire the delay data signal and the first delay clock signal when the signals are changed; a third variable delay circuit that delays the clock signal to output a second delay clock signal; a second delay adjusting section that adjusts a delay amount of the third variable delay circuit based on the acquired first delay clock signal of which a phase is adjusted by the first delay adjusting section when the second delay clock is changed, in order to adjust a phase differenc

Abstract: There is provided a test apparatus including a driver that outputs a test signal to a device under test, a first switch that switches whether to connect the driver to the device under test, a comparator that receives an output signal from the device under test via the first switch, and compares a voltage of the output signal with a predetermined reference voltage, a reference voltage input section that inputs the reference voltage into the comparator, a second switch that is provided between the reference voltage input section and the comparator, and a dummy resistance that is connected at one end thereof to a connection point between the comparator and the second switch and at the other end thereof to a predetermined potential. Here, a resistance ratio between an output resistance of the driver and an on-resistance of the first switch is substantially equal to a resistance ratio between the dummy resistance and an on-resistance of the second switch.

Abstract: Provided is a test apparatus that tests a DUT, which includes a driver that outputs a test signal to the DUT, a first transmission path that electrically connects the driver and the DUT, a first FET switch provided on the first transmission path to connect or disconnect the driver and the DUT to or from each other, and a capacitance compensator that detects an output signal from the DUT, and charges or discharges a capacitive component of the first FET switch based on the detected output signal.

Abstract: A driver circuit includes a main driver which receives an input signal and outputs a first signal corresponding to the input signal, a sub driver which receives the input signal and outputs a non-inverted signal and an inverted signal corresponding to the input signal, a differentiating circuit including resistors and a variable capacity condenser, which outputs signals by differentiating the non-inverted signal and the inverted signal, respectively, and an addition unit which outputs a high frequency emphasized signal given by adding the output signal of the main driver and the signal given by differentiating the non-inverted signal, or a low frequency emphasized signal given by adding the output signal of the main driver and the signal given by differentiating the inverted signal.

Abstract: A transmission line driving circuit that can support a high-rate signal transmission and further can perform appropriate loss compensation in accordance with a signal pattern. A transmission line driving circuit 1 comprises a plurality of driver input circuits 20 that serve as signal analyzing unit for analyzing the content of the signal pattern of an input signal; a plurality of lowpass filters 30; a plurality of gain adjusting circuits 40; a plurality of adders 50; and adder 52; and a driver output circuit 60 that outputs, in accordance with a signal analysis result, a signal the phase of which has been adjusted in such a direction that cancels the timing deviation caused by a loss occurring when the input signal is transmitted to the transmission path. The output signal from the driver output circuit 60 is transmitted to the transmission path 2.

Abstract: Provided is a driver circuit that includes a first operational mode and a second operational mode and outputs an output signal according to an input signal, including a first driver section that, in the first operational mode, generates and outputs the output signal according to the input signal and, in the second operational mode, outputs a power supply power having a predetermined voltage and a second driver section that, in the first operational mode, receives the output signal output by the first driver section and outputs the received signal to the outside and, in the second operational mode, generates the output signal according to the input signal and outputs the thus generated signal to the outside.

Abstract: Provided is a driver circuit that outputs a transmission signal according to a reception signal received from outside, including a first driver that outputs a voltage according to an input first signal; a second driver that receives the voltage output by the first driver as a power supply voltage and outputs the transmission signal according to the power supply voltage and an input second signal; and a control section that delays both the first signal and the second signal, according to a change of the reception signal, and causes the transmission signal according to the reception signal to be output from the second driver.

Abstract: There is provided an electronic device for receiving an input data signal and an input clock signal that indicates a timing to obtain the input data signal. The electronic device includes a first adjusting section that adjusts a phase difference between the input data signal and the input clock signal so as to be equal to a first phase difference, and outputs the resulting signals as a first data signal and a first clock signal, a phase varying section that outputs a second clock signal having a designated phase difference with respect to the first clock signal, and a second adjusting section that adjusts the phase difference of the second clock signal with respect to the first clock signal so as to be equal to a second phase difference, based on a result of obtaining the first clock signal at a varying timing of the second clock signal.

Abstract: The apparatus includes a first variable delay circuit that delays a data signal from a device under test (DUT) to output a delay data signal; a second variable delay circuit that delays a clock signal to output a first delay clock signal; a first FF that acquires the delay data signal based on a reference clock; a second FF that acquires the first delay clock signal based on the clock; a first delay adjusting section that adjusts a delay amount of at least one of the first and second variable delay circuits so that the first and second FFs acquire the delay data signal and the first delay clock signal when the signals are changed; a third variable delay circuit that delays the clock signal to output a second delay clock signal; a second delay adjusting section that adjusts a delay amount of the third variable delay circuit based on the acquired first delay clock signal of which a phase is adjusted by the first delay adjusting section when the second delay clock is changed, in order to adjust a phase differenc

Abstract: There is provided a test apparatus including a driver that outputs a test signal to a device under test, a first switch that switches whether to connect the driver to the device under test, a comparator that receives an output signal from the device under test via the first switch, and compares a voltage of the output signal with a predetermined reference voltage, a reference voltage input section that inputs the reference voltage into the comparator, a second switch that is provided between the reference voltage input section and the comparator, and a dummy resistance that is connected at one end thereof to a connection point between the comparator and the second switch and at the other end thereof to a predetermined potential. Here, a resistance ratio between an output resistance of the driver and an on-resistance of the first switch is substantially equal to a resistance ratio between the dummy resistance and an on-resistance of the second switch.