Patents by Inventor Takashi Shibasaki
Takashi Shibasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9363894Abstract: A compact circuit device wherein a semiconductor element that performs high current switching is embedded is provided. The hybrid integrated circuit device (10) is provided with: a circuit board (12); a plurality of ceramic substrates (22A-22G) disposed on the top surface of the circuit board (12); circuit elements such as transistors mounted on the top surface of the ceramic substrates (22A-22G); and a lead (29) or the like that is connected to the circuit elements and is exposed to the outside. Furthermore, in the present embodiment, leads (28, 30, 31A-31C) are disposed superimposed in the vicinity of the center of the circuit board (12), and a circuit element such as an IGBT is disposed and electrically connected approaching the region at which the leads are superimposed. The alternating current transformed by the IGBT is output externally via the leads (31A, etc.).Type: GrantFiled: September 15, 2011Date of Patent: June 7, 2016Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Takashi Shibasaki, Hidefumi Saito, Takahisa Makino, Masanori Shimizu, Daisuke Sasaki
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Patent number: 9362205Abstract: A compact circuit device wherein a semiconductor element that performs high current switching is embedded is provided. A lead (30) and lead (28) though which high current passes are disposed superimposed on the upper surface of a circuit board (12). Also, a plurality of ceramic substrates (22A-22F) are affixed to the circuit board (12), and transistors, diodes, or resistors are mounted to the upper surface of the ceramic substrates. Furthermore, the circuit elements such as the transistors or diodes are connected to the lead (28) or the other lead (30) via fine metal wires.Type: GrantFiled: September 15, 2011Date of Patent: June 7, 2016Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Takashi Shibasaki, Hidefumi Saito, Takahisa Makino, Masanori Shimizu, Daisuke Sasaki
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Patent number: 9271397Abstract: A circuit device having superior voltage resistance is provided. A structure is achieved that omits the resin layer that is normally provided to the top surface of a circuit board. Specifically, a ceramic substrate (22) is disposed on the top surface of a circuit board (12) comprising a metal, and a transistor (34) such as an IGBT is mounted to the top surface of the ceramic substrate (22). As a result, the transistor (34) and the circuit board (12) are insulated from each other by the ceramic substrate (22). The ceramic substrate (22), which comprises an inorganic material, has an extremely high voltage resistance compared to the conventionally used insulating layer comprising resin, and so even if a high voltage on the order of 1000V is applied to the transistor (34), short circuiting between the transistor (34) and the circuit board (12) is prevented.Type: GrantFiled: September 15, 2011Date of Patent: February 23, 2016Assignee: Semiconductor Components Industries, LLCInventors: Takashi Shibasaki, Hidefumi Saito, Takahisa Makino, Masanori Shimizu, Daisuke Sasaki
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Publication number: 20130286617Abstract: A compact circuit device wherein a semiconductor element that performs high current switching is embedded is provided. A lead (30) and lead (28) though which high current passes are disposed superimposed on the upper surface of a circuit board (12). Also, a plurality of ceramic substrates (22A-22F) are affixed to the circuit board (12), and transistors, diodes, or resistors are mounted to the upper surface of the ceramic substrates. Furthermore, the circuit elements such as the transistors or diodes are connected to the lead (28) or the other lead (30) via fine metal wires.Type: ApplicationFiled: September 15, 2011Publication date: October 31, 2013Applicant: ON Semiconductor Trading, Ltd.Inventors: Takashi Shibasaki, Hidefumi Saito, Takahisa Makino, Masanori Shimizu, Daisuke Sasaki
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Publication number: 20130286616Abstract: A circuit device having superior voltage resistance is provided. A structure is achieved that omits the resin layer that is normally provided to the top surface of a circuit board. Specifically, a ceramic substrate (22) is disposed on the top surface of a circuit board (12) comprising a metal, and a transistor (34) such as an IGBT is mounted to the top surface of the ceramic substrate (22). As a result, the transistor (34) and the circuit board (12) are insulated from each other by the ceramic substrate (22). The ceramic substrate (22), which comprises an inorganic material, has an extremely high voltage resistance compared to the conventionally used insulating layer comprising resin, and so even if a high voltage on the order of 1000V is applied to the transistor (34), short circuiting between the transistor (34) and the circuit board (12) is prevented.Type: ApplicationFiled: September 15, 2011Publication date: October 31, 2013Applicant: ON Semiconductor Trading, Ltd.Inventors: Takashi Shibasaki, Hidefumi Saito, Takahisa Makino, Masanori Shimizu, Daisuke Sasaki
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Publication number: 20130286618Abstract: A compact circuit device wherein a semiconductor element that performs high current switching is embedded is provided. The hybrid integrated circuit device (10) is provided with: a circuit board (12); a plurality of ceramic substrates (22A-22G) disposed on the top surface of the circuit board (12); circuit elements such as transistors mounted on the top surface of the ceramic substrates (22A-22G); and a lead (29) or the like that is connected to the circuit elements and is exposed to the outside. Furthermore, in the present embodiment, leads (28, 30, 31A-31C) are disposed superimposed in the vicinity of the center of the circuit board (12), and a circuit element such as an IGBT is disposed and electrically connected approaching the region at which the leads are superimposed. The alternating current transformed by the IGBT is output externally via the leads (31A, etc.).Type: ApplicationFiled: September 15, 2011Publication date: October 31, 2013Applicant: ON Semiconductor Trading, Ltd.Inventors: Takashi Shibasaki, Hidefumi Saito, Takahisa Makino, Masanori Shimizu, Daisuke Sasaki
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Patent number: 8373197Abstract: Provided is a circuit device having a configuration in which thermal interference between built-in elements is suppressed and being miniaturized in total size. A hybrid integrated circuit device of the present invention includes: a circuit substrate, a sealing resin and leads. The circuit substrate in its upper surface is incorporated with a hybrid integrated circuit formed of semiconductor elements and the like respectively fixed to heat spreaders. The sealing resin coats the circuit substrate and thus seals the hybrid integrated circuit. The leads each extend to the outside while being fixed to a pad formed of a conductive pattern. In this hybrid integrated circuit device, the semiconductor elements are mounted on the respective heat spreaders at positions offset from each other, and thereby are arranged to be spaced away from each other.Type: GrantFiled: September 28, 2009Date of Patent: February 12, 2013Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLCInventors: Kiyoaki Kudo, Takashi Shibasaki, Tetsuya Yamamoto
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Patent number: 8061130Abstract: An exhaust manifold A includes, in its collecting part structure, a plurality of branch pipes 2 to 5 that are connected with a flange head 1, a collecting part 6 that collects and contains exhaust-gas downstream side end portions 2a to 5a of the branch pipes 2 to 5, a partition plate 10 that is arranged in a state where its exhaust-gas downstream side end portion 10a projects in the interior of the collecting part 6, and a sensor attachment boss part 9 that is fixed by weld line X on a part of an outer circumferential portion of the collecting part 6 in a state where it faxes an insertion hole 6f formed in the collecting part 6.Type: GrantFiled: June 25, 2007Date of Patent: November 22, 2011Assignee: Calsonic Kansei CorporationInventor: Takashi Shibasaki
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Publication number: 20100078675Abstract: Provided is a circuit device having a configuration in which thermal interference between built-in elements is suppressed and being miniaturized in total size. A hybrid integrated circuit device of the present invention includes: a circuit substrate, a sealing resin and leads. The circuit substrate in its upper surface is incorporated with a hybrid integrated circuit formed of semiconductor elements and the like respectively fixed to heat spreaders. The sealing resin coats the circuit substrate and thus seals the hybrid integrated circuit. The leads each extend to the outside while being fixed to a pad formed of a conductive pattern. In this hybrid integrated circuit device, the semiconductor elements are mounted on the respective heat spreaders at positions offset from each other, and thereby are arranged to be spaced away from each other.Type: ApplicationFiled: September 28, 2009Publication date: April 1, 2010Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.Inventors: Kiyoaki KUDO, Takashi SHIBASAKI, Tetsuya YAMAMOTO
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Publication number: 20090288405Abstract: An exhaust manifold A includes, in its collecting part structure, a plurality of branch pipes 2 to 5 that are connected with a flange head 1, a collecting part 6 that collects and contains exhaust-gas downstream side end portions 2a to 5a of the branch pipes 2 to 5, a partition plate 10 that is arranged in a state where its exhaust-gas downstream side end portion 10a projects in the interior of the collecting part 6, and a sensor attachment boss part 9 that is fixed by weld line X on a part of an outer circumferential portion of the collecting part 6 in a state where it faxes an insertion hole 6f formed in the collecting part 6.Type: ApplicationFiled: June 25, 2007Publication date: November 26, 2009Inventor: Takashi Shibasaki