Abstract: A semiconductor device includes: a semiconductor substrate; a plurality of first pad electrodes provided above the semiconductor substrate; a plurality of first wires electrically connected to the plurality of first pad electrodes respectively; a first electrode commonly connected to the plurality of first wires; a second pad electrode provided above the semiconductor substrate; and a first resistance portion and a first protective element that are connected in series between the first electrode and the second pad electrode.

Abstract: A semiconductor device includes: a semiconductor substrate; a plurality of first pad electrodes provided above the semiconductor substrate; a plurality of first wires electrically connected to the plurality of first pad electrodes respectively; a first electrode commonly connected to the plurality of first wires; a second pad electrode provided above the semiconductor substrate; and a first resistance portion and a first protective element that are connected in series between the first electrode and the second pad electrode.

Abstract: A resistance change memory includes a first conductive line extending in a first direction, a second conductive line extending in a second direction which is crossed to the first direction, a cell unit including a memory element and a rectifying element connected in series between the first and second conductive lines, and a control circuit which is connected to both of the first and second conductive lines. The control circuit controls a voltage to change a resistance of the memory element between first and second values reversibly. The rectifying element is a diode including an anode layer, a cathode layer and an insulating layer therebetween.

Abstract: A resistance change memory includes a first conductive line extending in a first direction, a second conductive line extending in a second direction which is crossed to the first direction, a cell unit including a memory element and a rectifying element connected in series between the first and second conductive lines, and a control circuit which is connected to both of the first and second conductive lines. The control circuit controls a voltage to change a resistance of the memory element between first and second values reversibly. The rectifying element is a diode including an anode layer, a cathode layer and an insulating layer therebetween.

Abstract: A semiconductor memory device in an embodiment comprises memory cells, each of the memory cells disposed between a first line and a second line and having a variable resistance element and a switching element connected in series. The variable resistance element includes a variable resistance layer configured to change in resistance value thereof between a low-resistance state and a high-resistance state. The variable resistance layer is configured by a transition metal oxide. A ratio of transition metal and oxygen configuring the transition metal oxide varies between 1:1 and 1:2 along a first direction directed from the first line to the second line.

Abstract: A nonvolatile semiconductor memory device according to an embodiment herein includes a memory cell array. The memory cell array includes memory cells each provided between a first line and a second line and each including a variable resistor. A control circuit applies through the first and second lines a voltage necessary for a forming operation of the memory cell. A current limiting circuit limits a value of a current flowing across the memory cell during the forming operation to a certain limit value. The control circuit repeats an operation of applying the voltage by setting the limit value to a certain value and an operation of changing the limit value from the certain value, until forming of the memory cell is achieved.

Abstract: A resistance change memory includes a first conductive line extending in a first direction, a second conductive line extending in a second direction which is crossed to the first direction, a cell unit including a memory element and a rectifying element connected in series between the first and second conductive lines, and a control circuit which is connected to both of the first and second conductive lines. The control circuit controls a voltage to change a resistance of the memory element between first and second values reversibly. The rectifying element is a diode including an anode layer, a cathode layer and an insulating layer therebetween.

Abstract: A semiconductor memory device according to an embodiment includes: first lines provided on a substrate; second lines provided between the first lines and the substrate so as to intersect the first lines; and a first memory cell array including first memory cells, each of the first memory cells being provided at respective intersections of the first lines and the second lines and including a current rectifying element and a variable resistor connected in series. The variable resistor of the first memory cell includes a first recording layer and a second recording layer, the first recording layer being made of an oxide of a first metal material, the second recording layer being made of the first metal material and being formed so as to contact with the first recording layer. The second recording layer is closer to the first line than the first recording layer is.

Abstract: A semiconductor memory device in an embodiment comprises memory cells, each of the memory cells disposed between a first line and a second line and having a variable resistance element and a switching element connected in series. The variable resistance element includes a variable resistance layer configured to change in resistance value thereof between a low-resistance state and a high-resistance state. The variable resistance layer is configured by a transition metal oxide. A ratio of transition metal and oxygen configuring the transition metal oxide varies between 1:1 and 1:2 along a first direction directed from the first line to the second line.

Abstract: A substrate processing unit comprises a processing vessel for receiving a substrate, a cleaning gas supply system for supplying cleaning gas to the processing vessel so as to clean the interior of the processing vessel, an exhauster for exhausting the processing vessel, an operating state detector for detecting the operating state of the exhauster, and an end point detector for detecting the end point of the cleaning on the basis of the detection result from the operating state detector.

Abstract: A nonvolatile semiconductor memory device according to an embodiment herein includes a memory cell array. The memory cell array includes memory cells each provided between a first line and a second line and each including a variable resistor. A control circuit applies through the first and second lines a voltage necessary for a forming operation of the memory cell. A current limiting circuit limits a value of a current flowing across the memory cell during the forming operation to a certain limit value. The control circuit repeats an operation of applying the voltage by setting the limit value to a certain value and an operation of changing the limit value from the certain value, until forming of the memory cell is achieved.

Abstract: According to one embodiment, a nonvolatile memory device including a nonvolatile memory layer is provided. The nonvolatile memory layer is formed of a metal oxide film that includes an element with a higher electronegativity compared with a metal element forming the metal oxide film in the metal oxide film at a concentration of 25 at % or less.

Abstract: According to one embodiment, a nonvolatile memory device is provided, which includes a nonvolatile memory element in which an anode, a nonvolatile memory layer formed of a metal oxide film, and a cathode are stacked. The anode is formed of a metal nitride material and includes nitrogen more than a stoichiometric ratio of the metal nitride material. The cathode is formed of a metal material.

Abstract: A semiconductor memory device of an embodiment includes: a cathode electrode formed of a p-type semiconductor material; a resistance change film being in contact with the cathode electrode; and an anode electrode being contact with the resistance change film.

Abstract: A resistance change memory includes a first conductive line extending in a first direction, a second conductive line extending in a second direction which is crossed to the first direction, a cell unit including a memory element and a rectifying element connected in series between the first and second conductive lines, and a control circuit which is connected to both of the first and second conductive lines. The control circuit controls a voltage to change a resistance of the memory element between first and second values reversibly. The rectifying element is a diode including an anode layer, a cathode layer and an insulating layer therebetween.

Abstract: A processing apparatus is disclosed which is capable of switching supplies of a raw material gas and a reducing gas alternately, while continuously forming a plasma of the reducing gas. An excitation device (12) excites a reducing gas supplied thereinto, and the excited reducing gas is supplied into a process chamber (2). A switching mechanism (20) is arranged between the excitation device (12) and the process chamber (2), and a bypass line (22) is connected to the switching mechanism (20). The switching mechanism (20) switches the flow of the excited reducing gas from the excitation device (12) between the process chamber (2) and the bypass line (22).

Abstract: In a processing apparatus, a process gas including a source gas (TiCl4, NH3) and an inert gas (N2) is supplied into a process chamber (2). A pressure meter (6) detects a pressure in the process chamber (2) so as to control an amount of flow of the process gas supplied to the process chamber (2) based on a result of the detection. A source gas is purged by the inert gas. By maintaining the amount of flow of the source gas constant and controlling the amount of flow of the inert gas, an amount of flow the entire process gas is controlled so as to maintain a pressure in the process chamber (2) constant. Since a time spent on evacuation of the source gas is reduced, a time for switching the source gas is reduced. Additionally, a temperature of a surface of a substrate during processing can be maintained constant.

Abstract: A semiconductor device includes a semiconductor substrate, a first memory cell transistor, a first select gate transistor, a second memory cell transistor, a second select gate transistor, a contact plug, silicon oxide films, and plasma films which are formed as the same layer as the silicon oxide films and are provided above upper surfaces of the first and the third gate electrodes.

Abstract: A semiconductor memory according to an aspect of this invention comprises a semiconductor substrate which includes a memory cell array region and an interconnect line region adjoining the memory cell array region, memory cells which are provided in the memory cell array region, contact plugs which are provided in the interconnect line region, and control gate lines which are provided so as to extend from the interconnect line region to the memory cell array region and which connect the contact plugs with the memory cells, wherein the control gate lines provided in the memory cell array region include metal silicide and the control gate lines provided in the interconnect line region include no metal silicide at any part of the interconnect line region.

Abstract: A method of rapidly forming a thin film of high quality through film formation by alternate feeding of raw gases. In particular, a method of forming a TiN thin film, comprising repeating operations including causing TiCl4 gas as a raw gas to be adsorbed on a substrate or TiCl4 molecules adsorbed on a substrate and feeding NH3 gas as a reactant gas in a treating chamber so as to effect reaction of TiCl4 and NH3 leading to formation of a TiN film, which method further comprises an operation of, prior to the adsorption of TiCl4 gas on the substrate, feeding reducing H2 gas in the treating chamber (30) so as to change TiCl4 to a state of enhanced likelihood of adsorption on the substrate (e.g., TiCl3).