Patents by Inventor Takashi Shiizaki

Takashi Shiizaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8416155
    Abstract: Provided is a technique of a PDP device capable of preventing error display arising from changes in discharge characteristics in a reset period particularly due to a long-period operation. In the PDP device, a slope of a slope waveform in the reset period is changed corresponding to operation time of the PDP device. And, the slope waveform is made to have a configuration having a stepwise plurality of slopes in a predetermined reset period. For example, when the operation time becomes long, rising and falling slope waveforms of a reset waveform are configured by two steps, and a first slope thereof is made steeper than a slope before the change, and a second slope is made gentle than the slope before the change. When the operation become longer, the first slope is made further steeper and the subsequent second slope is made further gentler.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: April 9, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuya Kaminaka, Takashi Shiizaki, Takashi Sasaki, Hirohito Kuriyama
  • Patent number: 8040295
    Abstract: In a PDP apparatus provided with a PDP having (X, Y, A) and various drivers, two adjacent Ys in a plurality of Ys are commonly connected by a wiring so as to form one set unit, in the vicinity of a connection portion of the PDP and the drivers. A two-stage reset and address operation control using a reset operation including an address disable operation is used for a control unit including a plurality of display lines (L) of the set units. In a plurality of Ls as objects of drive display, the reset and address operation of first Ls (Lo) corresponding to Ys on one side of set units and that of second Ls (Le) corresponding to Ys on the other side thereof are performed separately in former and latter periods, and then, sustain operations of the first and second Ls on both sides are performed simultaneously.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: October 18, 2011
    Assignee: Fujitsu Hitachi Plasma Display Limited
    Inventors: Akihiro Takagi, Tetsuya Sakamoto, Takashi Shiizaki
  • Patent number: 8009123
    Abstract: In the PDP device, for example, two types of SF lighting patterns (A and B modes) are equally divided and arranged in spatially different regions in a field. For example, the patterns are arranged in a zigzag manner in units of pixels. At all lighting steps, existence of an absence of light-on SF which becomes a cause of false contour is permitted only in one mode. Accordingly, a generation rate of absence of light-on SF per field when the modes are combined is low, and the level of false contour can be reduced. Further, the spatial arrangement of each mode is optionally changed among the fields.
    Type: Grant
    Filed: January 25, 2007
    Date of Patent: August 30, 2011
    Assignee: Fujitsu Hitachi Plasma Display Limited
    Inventors: Katsuhiro Ishida, Akira Yamamoto, Ayahito Kojima, Shingo Kubo, Takashi Shiizaki, Hirohito Kuriyama
  • Patent number: 7773052
    Abstract: There is provided a plasma display device including a slope waveform generating circuit which supplies to an electrode a slope waveform of which voltage changes with the lapse of time, the electrode being formed in a capacitive load to serves as a display element in a display panel for displaying images, wherein the slope waveform generating circuit includes: a plurality of power supplies which supply different voltages; and a switching circuit which selects one power supply out of the a plurality of power supplies and supplies a voltage to the electrode, wherein the switching circuit switches the power supply, which supplies a voltage to the electrode, in accordance with a voltage being supplied to the electrode.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: August 10, 2010
    Assignee: Fujitsu Hitachi Plasma Display Limited
    Inventors: Masaki Kamada, Takashi Shiizaki
  • Patent number: 7710042
    Abstract: A PDP apparatus comprises, in a circuit part, a ramp output device which outputs a ramp wave to electrodes of a PDP. The ramp output device has a ramp generator which generates and outputs a first ramp wave of which inclination is variable, an impedance conversion circuit which receives the first ramp wave as input and outputs a second ramp wave produced by impedance conversion, and a feedback circuit which receives the second ramp wave as input and feeds it back to the input of the ramp generator. The ramp generator outputs the second ramp wave as a ramp wave (output voltage). Techniques to realize output of stabilized ramp wave in a PDP apparatus so as to stabilize PDP display operations are provided.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: May 4, 2010
    Assignee: Fujitsu Hitachi Plasma Display Limited
    Inventors: Takashi Shiizaki, Masaki Kamada, Akihiro Machida, Sojiro Hagihara
  • Patent number: 7639213
    Abstract: A driving circuit of a plasma display panel is provided in which a display cell including a first electrode and a second electrode is selected to light up, for applying a first voltage Vs1 to the first electrode and a second voltage Vs2 to the second electrode adjacent to the first electrode to cause a sustain discharge between the first and second electrodes. The driving circuit generates a sustain discharge voltage such that, during the sustain discharge between the first and second electrodes, an applied voltage Vc to a third electrode adjacent to the first electrode opposite to the second electrode falls within a range Vs2?Vc<Vs1, and, in this case, when a display cell including the third electrode is selected to light up, the polarity of a wall charge formed on the third electrode becomes positive.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: December 29, 2009
    Assignee: Fujitsu Hitachi Plasma Display Limited
    Inventors: Akihiro Takagi, Takashi Shiizaki, Takayuki Shimizu, Noriaki Setoguchi, Hitoshi Hirakawa, Tomokatsu Kishi
  • Publication number: 20090040206
    Abstract: A driving method of a plasma display panel which performs image display using a plurality of sub-fields. In a sustain discharge period, a first sustain discharge waveform and a second sustain discharge waveform are applied, the second sustain discharge waveform having a timing of voltage clamping at a rising edge of a pulse which is earlier than that of the first sustain discharge waveform. In a predetermined sub-field in one frame, the first sustain discharge waveform is repeatedly applied without applying the second sustain discharge waveform, and in other sub-fields, the first sustain discharge waveform and the second sustain discharge waveform are repeatedly applied.
    Type: Application
    Filed: October 2, 2008
    Publication date: February 12, 2009
    Inventors: Takashi Shiizaki, Katsuhiro Ishida
  • Publication number: 20080278413
    Abstract: A plasma display apparatus includes a plurality of electrodes and a driver circuit configured to drive the plurality of electrodes, wherein the driver circuit includes a plurality of driver ICs coupled in common to an electrode with respect to each of the plurality of electrodes, and the plurality of driver ICs supply electric currents to said electrode in a temporally staggered manner so as to drive each of the plurality of electrodes.
    Type: Application
    Filed: October 18, 2007
    Publication date: November 13, 2008
    Inventors: Takashi Shiizaki, Hidenori Ohnuki, Satoshi Yuri, Tetsuya Kaminaka, Hirohito Kuriyama, Tomokatsu Kishi
  • Publication number: 20080048942
    Abstract: In the PDP device, for example, two types of SF lighting patterns (A and B modes) are equally divided and arranged in spatially different regions in a field. For example, the patterns are arranged in a zigzag manner in units of pixels. At all lighting steps, existence of an absence of light-on SF which becomes a cause of false contour is permitted only in one mode. Accordingly, a generation rate of absence of light-on SF per field when the modes are combined is low, and the level of false contour can be reduced. Further, the spatial arrangement of each mode is optionally changed among the fields.
    Type: Application
    Filed: January 25, 2007
    Publication date: February 28, 2008
    Inventors: Katsuhiro Ishida, Akira Yamamoto, Ayahito Kojima, Shingo Kubo, Takashi Shiizaki, Hirohito Kuriyama
  • Publication number: 20080025057
    Abstract: A PDP apparatus comprises, in a circuit part, a ramp output device which outputs a ramp wave to electrodes of a PDP. The ramp output device has a ramp generator which generates and outputs a first ramp wave of which inclination is variable, an impedance conversion circuit which receives the first ramp wave as input and outputs a second ramp wave produced by impedance conversion, and a feedback circuit which receives the second ramp wave as input and feeds it back to the input of the ramp generator. The ramp generator outputs the second ramp wave as a ramp wave (output voltage). Techniques to realize output of stabilized ramp wave in a PDP apparatus so as to stabilize PDP display operations are provided.
    Type: Application
    Filed: February 7, 2007
    Publication date: January 31, 2008
    Inventors: Takashi Shiizaki, Masaki Kamada, Akihiro Machida, Sojiro Hagihara
  • Publication number: 20070236417
    Abstract: In a PDP apparatus provided with a PDP having (X, Y, A) and various drivers, two adjacent Ys in a plurality of Ys are commonly connected by a wiring so as to form one set unit, in the vicinity of a connection portion of the PDP and the drivers. A two-stage reset and address operation control using a reset operation including an address disable operation is used for a control unit including a plurality of display lines (L) of the set units. In a plurality of Ls as objects of drive display, the reset and address operation of first Ls (Lo) corresponding to Ys on one side of set units and that of second Ls (Le) corresponding to Ys on the other side thereof are performed separately in former and latter periods, and then, sustain operations of the first and second Ls on both sides are performed simultaneously.
    Type: Application
    Filed: February 7, 2007
    Publication date: October 11, 2007
    Inventors: Akihiro Takagi, Tetsuya Sakamoto, Takashi Shiizaki
  • Publication number: 20070200799
    Abstract: A flat panel display device includes switching elements QA3 and QA4, respectively connected to a voltage Vs and ground to be applied to a panel capacitance Cp when performing light emission relating to image display, for clamping the voltage of the panel capacitance; coils LA1 and LA2 each having one end connected to the panel capacitance; a path separation circuit DLA1 and DLA2, connected to the other ends of the coils, for separating paths through which charge/discharge currents flow; a switching element QA1 connected between the voltage Vs and the path separation circuit; a switching element QA2 connected between the ground and the path separation circuit; and diodes connected in parallel to the switching elements, in which the resonance reference voltage relating to a power recovery operation is set to a maximum voltage and a minimum voltage to be applied to the panel capacitance, and the paths through which the charge/discharge currents flow are separated to thereby improve the recovery efficiency in a p
    Type: Application
    Filed: November 21, 2006
    Publication date: August 30, 2007
    Inventors: Hideaki Ohki, Akira Otsuka, Sojiro Hagihara, Takashi Shiizaki, Makoto Onozawa
  • Patent number: 7230587
    Abstract: In a plasma display device having a reduced discharge-current-induced voltage fluctuation and an expanded drive margin and being successful in preventing the display characteristics from being degraded, a Y-electrode drive circuit and an X-electrode drive circuit for supplying a drive voltage to the capacitance which represents a display cell are configured using parallel circuits in which first switching elements having a high-speed-switching performance and second switching elements having a low-saturation-voltage performance are connected in parallel, so that the second switching elements having the low-saturation-voltage performance are turned on at least during a period that discharge current flows therebetween.
    Type: Grant
    Filed: February 19, 2004
    Date of Patent: June 12, 2007
    Assignee: Fujitsu Hitachi Plasma Display Limited
    Inventors: Makoto Onozawa, Hideaki Ohki, Masaki Kamada, Takashi Shiizaki
  • Publication number: 20070057870
    Abstract: There is provided a plasma display device including a slope waveform generating circuit which supplies to an electrode a slope waveform of which voltage changes with the lapse of time, the electrode being formed in a capacitive load to serves as a display element in a display panel for displaying images, wherein the slope waveform generating circuit includes: a plurality of power supplies which supply different voltages; and a switching circuit which selects one power supply out of the a plurality of power supplies and supplies a voltage to the electrode, wherein the switching circuit switches the power supply, which supplies a voltage to the electrode, in accordance with a voltage being supplied to the electrode.
    Type: Application
    Filed: September 5, 2006
    Publication date: March 15, 2007
    Applicant: FUJITSU HITACHI PLASMA DISPLAY LIMITED
    Inventors: Masaki Kamada, Takashi Shiizaki
  • Patent number: 7145526
    Abstract: A driving circuit of a plasma display panel is provided in which a display cell including a first electrode and a second electrode is selected to light up, for applying a first voltage Vs1 to the first electrode and a second voltage Vs2 to the second electrode adjacent to the first electrode to cause a sustain discharge between the first and second electrodes. The driving circuit generates a sustain discharge voltage such that, during the sustain discharge between the first and second electrodes, an applied voltage Vc to a third electrode adjacent to the first electrode opposite to the second electrode falls within a range Vs2?Vc<Vs1, and, in this case, when a display cell including the third electrode is selected to light up, the polarity of a wall charge formed on the third electrode becomes positive.
    Type: Grant
    Filed: May 19, 2003
    Date of Patent: December 5, 2006
    Assignee: Fujitsu Hitachi Plasma Display Limited
    Inventors: Akihiro Takagi, Takashi Shiizaki, Takayuki Shimizu, Noriaki Setoguchi, Hitoshi Hirakawa, Tomokatsu Kishi
  • Patent number: 7142176
    Abstract: A method of driving a plasma display panel, which includes controlling a charge state of a first display line being one of the two adjacent display lines utilizing the same single scan electrode, such that address discharge is not generated and controlling a charge state of a second display line being the other of the two adjacent display lines, such that address discharge can be generated, and then generating address discharge in the second display line, controlling the charge state of the second display line such that address discharge is not generated and controlling the charge state of the first display line such that the address discharge can be generated, and then generating address discharge in the first display line, and generating surface discharge simultaneously in the first and second display lines, thereby to achieve progressive display.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: November 28, 2006
    Assignee: Fujitsu Hitachi Plasma Display Limited
    Inventors: Takashi Shiizaki, Hitoshi Hirakawa
  • Patent number: 7123217
    Abstract: A driving method of a plasma display panel is provided in which effective resolution and luminance in a display of fields that constitute a frame are improved. The method includes dividing each of M (M?2) fields that constitute a frame into K (K?2) subfields having luminance weight, displaying the k (1?k<K) subfields selected in descending order of the luminance weight in progressive format using all display lines out of the K subfields and displaying the remaining subfields in interlaced format using the display lines selected at regular intervals at a ratio of one per M display lines in arrangement order.
    Type: Grant
    Filed: February 11, 2003
    Date of Patent: October 17, 2006
    Assignee: Fujitsu Hitachi Plasma Display Limited
    Inventors: Yoshimi Kawanami, Yasuhiko Kunii, Hitoshi Hirakawa, Takashi Shiizaki
  • Patent number: 7116288
    Abstract: A driving method of a plasma display panel having a display electrodes arranged at the ratio of three per two rows is provided, in which all rows are lighted in sustaining period from an addressing period to the next addressing period and electromagnetic interference is reduced sufficiently. A display discharge is generated by controlling potentials of the display electrodes so as to satisfy two conditions. One condition is that there is a pair of display electrodes having terminals at the same side of the display screen and current directions opposite to each other. Another condition is to generate a potential difference across the display electrodes, which is necessary for discharging. Magnetic fields are canceled by each other in the pair of electrodes having current directions opposite to each other, so that electromagnetic interference is reduced.
    Type: Grant
    Filed: June 21, 2001
    Date of Patent: October 3, 2006
    Assignee: Fujitsu Hitachi Plasma Display Limited
    Inventors: Takashi Shiizaki, Hitoshi Hirakawa
  • Publication number: 20060214884
    Abstract: In a conventional plasma display panel driving method, all sub-frames each require a driving sequence for resetting a charge, thereby increasing a background light-emission intensity and reducing contrast. A plasma display panel driving method according to the present invention comprises the steps of: configuring one frame by a plurality of sub-frames, and setting, for each of the sub-frames, an address period for using every other one of the display electrodes as a scan electrode to cause the address discharge to occur by the scan electrode and the address electrode, and a display period for causing a surface discharge to occur between the display electrodes; and in at least two sub-frames of the plurality of sub-frames configuring one frame, causing a discharge to occur in only one of two display lines sharing one scan electrode in the address period and the display period.
    Type: Application
    Filed: March 23, 2006
    Publication date: September 28, 2006
    Inventors: Takashi Shiizaki, Katsuhiro Ishida
  • Publication number: 20060214887
    Abstract: Conventionally, in an image display apparatus for gray-scale representation with two fields by a multiple gray-scaling scheme in which selective On-states in an odd field and an even field are made to differ, there has been a problem of deterioration in image quality due to occurrence of motion noise and flicker, for example. An image display method, in which a picture of one frame is configured by a plurality of sub-fields with different light-emitting display luminance levels, different selective On-states are capable of making to differ in accordance with display date inputted to an odd field and an even field, and a dither pattern for adding an arbitrary amount of data is capable of being inserted in accordance with the inputted display data, comprises the step of, for sorting the selective On-states in the odd and even fields and sorting the dither pattern, making at least one of a horizontal direction and a vertical direction to differ.
    Type: Application
    Filed: March 24, 2006
    Publication date: September 28, 2006
    Inventors: Katsuhiro Ishida, Takashi Shiizaki, Akira Yamamoto, Shigeharu Asao