Patents by Inventor Takashi Shingu
Takashi Shingu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11932336Abstract: A method of properly aligning a sliding side door on a vehicle includes first preparing a prototype vehicle and determining how far out of alignment the door is to the body of the prototype vehicle. This amount of misalignment is then used to adjust the attachment position of an anchor plate to a sliding side door of the vehicle, so that the anchor plate is attached at a desired position to the production vehicle, which causes there to be no misalignment between the sliding side door and the body of the production vehicle. A jig is used to hold the anchor plate at the desired location while welding the anchor plate to the door. A roller assembly is then attached to the anchor plate and to a rail on a body of the vehicle.Type: GrantFiled: December 22, 2022Date of Patent: March 19, 2024Assignee: HONDA MOTOR CO., LTD.Inventors: Hiroshi Shingu, Joji Goto, Takashi Fukahori, Yuichiro Saiki, Masatoshi Adachi, Christopher T. Laue, Khang C. Nguyen, Kenichiro Kagawa, Makoto Ono, Sunao Tachiki
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Publication number: 20230329105Abstract: An organic semiconductor device that can achieve high resolution and favorable reliability is provided. The organic semiconductor device is one of a plurality of light-emitting devices formed over an insulating layer, which includes a first electrode, a second electrode, and an organic compound layer. The organic compound layer is positioned between the first electrode and the second electrode. The organic compound layer includes a layer containing a first compound. When differential scanning calorimetry is performed on the first compound in such a manner that a cooling step is performed from the state in which the first compound is melted in a first heating step and a second heating step is successively performed, an exothermic peak is not observed in the cooling step and an exothermic peak and a melting point peak are not observed in the second heating step.Type: ApplicationFiled: April 4, 2023Publication date: October 12, 2023Inventors: Satoko NUMATA, Harue OSAKA, Sachiko KAWAKAMI, Takashi SHINGU, Anna TADA, Yui YOSHIYASU, Yasuhiro NIIKURA, Eriko AOYAMA, Naoaki HASHIMOTO, Satoshi SEO
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Patent number: 8815657Abstract: After a single crystal semiconductor layer provided over a base substrate by attaching is irradiated with a laser beam, characteristics thereof are improved by first heat treatment, and after adding an impurity element imparting conductivity to the single crystal semiconductor layer, second heat treatment is performed at lower temperature than that of the first heat treatment.Type: GrantFiled: August 31, 2009Date of Patent: August 26, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Suguru Ozawa, Atsuo Isobe, Takashi Hamada, Junpei Momo, Hiroaki Honda, Takashi Shingu, Tetsuya Kakehata
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Patent number: 8664722Abstract: In a method for manufacturing a semiconductor device, a semiconductor film formed over an insulator is doped with an impurity element to a depth less than the thickness of the semiconductor film, thereby forming an impurity doped layer; a metal silicide layer is formed on the impurity doped layer; the metal silicide layer and the semiconductor film are etched to form a recessed portion; and a layer which is not doped with the impurity element and is located at the bottom of the recessed portion of the semiconductor film is thinned to make a channel formation region. Further, a gate electrode is formed in the recessed portion over the thinned non impurity doped layer, with an insulating film interposed therebetween.Type: GrantFiled: November 4, 2011Date of Patent: March 4, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takashi Shingu, Daisuke Ohgarane, Yurika Sato
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Patent number: 8415228Abstract: To provide a manufacturing method of a semiconductor device in which, even when the semiconductor device is formed over an SOI substrate which uses a glass substrate, an insulating film and a semiconductor film over the glass substrate are not peeled by stress applied by a conductive film in formation of the conductive film for forming a gate electrode.Type: GrantFiled: September 9, 2009Date of Patent: April 9, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kazuya Hanaoka, Takashi Shingu, Taichi Endo
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Patent number: 8253252Abstract: It is an object to provide an element structure of a semiconductor device for having a sufficient contact area between an electrode in contact with a source region or a drain region and the source region or the drain region, and a method for manufacturing the semiconductor device with the element structure. An upper electrode is formed over a high-concentration impurity region (the source region or the drain region). A contact hole passing through an interlayer insulating film is formed overlapping with a region where the upper electrode and the high-concentration impurity region are stacked.Type: GrantFiled: March 19, 2008Date of Patent: August 28, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takashi Shingu, Hideki Matsukura
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Patent number: 8236668Abstract: An object of the present invention is to provide a method for manufacturing an SOI substrate provided with a semiconductor layer which can be used practically even where a substrate having a low upper temperature limit such as a glass substrate is used. The manufacturing method compromises the steps of preparing a semiconductor substrate provided with a bonding layer formed on a surface thereof and a separation layer formed at a predetermined depth from the surface thereof, bonding the bonding layer to the base substrate having a distortion point of 700° C. or lower so that the semiconductor substrate and the base substrate face each other, and separating a part of the semiconductor substrate at the separation layer by heat treatment in order to form a single-crystal semiconductor layer over the base substrate. In the manufacturing method, a substrate which shrinks isotropically at least by the heat treatment is used as the base substrate.Type: GrantFiled: October 2, 2008Date of Patent: August 7, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideto Ohnuma, Takashi Shingu, Tetsuya Kakehata, Kazutaka Kuriki, Shunpei Yamazaki
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Publication number: 20120049276Abstract: In a method for manufacturing a semiconductor device, a semiconductor film formed over an insulator is doped with an impurity element to a depth less than the thickness of the semiconductor film, thereby forming an impurity doped layer; a metal silicide layer is formed on the impurity doped layer; the metal silicide layer and the semiconductor film are etched to form a recessed portion; and a layer which is not doped with the impurity element and is located at the bottom of the recessed portion of the semiconductor film is thinned to make a channel formation region. Further, a gate electrode is formed in the recessed portion over the thinned non impurity doped layer, with an insulating film interposed therebetween.Type: ApplicationFiled: November 4, 2011Publication date: March 1, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Takashi SHINGU, Daisuke Ohgarane, Yurika Sato
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Patent number: 8053289Abstract: In a method for manufacturing a semiconductor device, a semiconductor film formed over an insulator is doped with an impurity element to a depth less than the thickness of the semiconductor film, thereby forming an impurity doped layer; a metal silicide layer is formed on the impurity doped layer; the metal silicide layer and the semiconductor film are etched to form a recessed portion; and a layer which is not doped with the impurity element and is located at the bottom of the recessed portion of the semiconductor film is thinned to make a channel formation region. Further, a gate electrode is formed in the recessed portion over the thinned non impurity doped layer, with an insulating film interposed therebetween.Type: GrantFiled: October 15, 2008Date of Patent: November 8, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takashi Shingu, Daisuke Ohgarane, Yurika Sato
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Patent number: 8048749Abstract: A method for manufacturing a semiconductor device, by which a bottom gate thin film transistor that has an improved S value and a channel forming region with a smaller thickness than that of a source region and a drain region can be manufactured in a simple process. An island-like conductive film is formed over a surface of an insulating substrate in a portion corresponding to a channel forming region, and is covered with an insulating film to form a projection portion. After an amorphous semiconductor film is deposited to cover the projection portion, the amorphous semiconductor film is irradiated with laser light so as to be melted and crystallized. Part of the melted semiconductor over the projection portion flows into regions adjacent to both sides of the projection portion, which results in reduction in thickness of the semiconductor film over the projection portion (channel forming region).Type: GrantFiled: July 23, 2008Date of Patent: November 1, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tomokazu Yokoi, Atsuo Isobe, Motomu Kurata, Takeshi Shichi, Daisuke Ohgarane, Takashi Shingu
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Publication number: 20100075470Abstract: After a single crystal semiconductor layer provided over a base substrate by attaching is irradiated with a laser beam, characteristics thereof are improved by first heat treatment, and after adding an impurity element imparting conductivity to the single crystal semiconductor layer, second heat treatment is performed at lower temperature than that of the first heat treatment.Type: ApplicationFiled: August 31, 2009Publication date: March 25, 2010Inventors: Suguru OZAWA, Atsuo ISOBE, Takashi HAMADA, Junpei MOMO, Hiroaki HONDA, Takashi SHINGU, Tetsuya KAKEHATA
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Publication number: 20100062583Abstract: To provide a manufacturing method of a semiconductor device in which, even when the semiconductor device is formed over an SOI substrate which uses a glass substrate, an insulating film and a semiconductor film over the glass substrate are not peeled by stress applied by a conductive film in formation of the conductive film for forming a gate electrode.Type: ApplicationFiled: September 9, 2009Publication date: March 11, 2010Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Kazuya HANAOKA, Takashi SHINGU, Taichi ENDO
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Publication number: 20090098739Abstract: An object of the present invention is to provide a method for manufacturing an SOI substrate provided with a semiconductor layer which can be used practically even where a substrate having a low upper temperature limit such as a glass substrate is used. The manufacturing method compromises the steps of preparing a semiconductor substrate provided with a bonding layer formed on a surface thereof and a separation layer formed at a predetermined depth from the surface thereof, bonding the bonding layer to the base substrate having a distortion point of 700° C. or lower so that the semiconductor substrate and the base substrate face each other, and separating a part of the semiconductor substrate at the separation layer by heat treatment in order to form a single-crystal semiconductor layer over the base substrate. In the manufacturing method, a substrate which shrinks isotropically at least by the heat treatment is used as the base substrate.Type: ApplicationFiled: October 2, 2008Publication date: April 16, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hideto OHNUMA, Takashi SHINGU, Tetsuya KAKEHATA, Kazutaka KURIKI, Shunpei YAMAZAKI
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Publication number: 20090096024Abstract: In a method for manufacturing a semiconductor device, a semiconductor film formed over an insulator is doped with an impurity element to a depth less than the thickness of the semiconductor film, thereby forming an impurity doped layer; a metal silicide layer is formed on the impurity doped layer; the metal silicide layer and the semiconductor film are etched to form a recessed portion; and a layer which is not doped with the impurity element and is located at the bottom of the recessed portion of the semiconductor film is thinned to make a channel formation region. Further, a gate electrode is formed in the recessed portion over the thinned non impurity doped layer, with an insulating film interposed therebetween.Type: ApplicationFiled: October 15, 2008Publication date: April 16, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Takashi SHINGU, Daisuke OHGARANE, Yurika SATO
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Publication number: 20090029514Abstract: A method for manufacturing a semiconductor device, by which a bottom gate thin film transistor that has an improved S value and a channel forming region with a smaller thickness than that of a source region and a drain region can be manufactured in a simple process. An island-like conductive film is formed over a surface of an insulating substrate in a portion corresponding to a channel forming region, and is covered with an insulating film to form a projection portion. After an amorphous semiconductor film is deposited to cover the projection portion, the amorphous semiconductor film is irradiated with laser light so as to be melted and crystallized. Part of the melted semiconductor over the projection portion flows into regions adjacent to both sides of the projection portion, which results in reduction in thickness of the semiconductor film over the projection portion (channel forming region).Type: ApplicationFiled: July 23, 2008Publication date: January 29, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Tomokazu YOKOI, Atsuo ISOBE, Motomu KURATA, Takeshi SHICHI, Daisuke OHGARANE, Takashi SHINGU
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Publication number: 20080230835Abstract: It is an object to provide an element structure of a semiconductor device for having a sufficient contact area between an electrode in contact with a source region or a drain region and the source region or the drain region, and a method for manufacturing the semiconductor device with the element structure. An upper electrode is formed over a high-concentration impurity region (the source region or the drain region). A contact hole passing through an interlayer insulating film is formed overlapping with a region where the upper electrode and the high-concentration impurity region are stacked.Type: ApplicationFiled: March 19, 2008Publication date: September 25, 2008Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Takashi Shingu, Hideki Matsukura