Patents by Inventor Takashi Shirono
Takashi Shirono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10818501Abstract: A method for manufacturing a semiconductor device includes bonding a supporting substrate and a first surface of a semiconductor substrate via a bonding layer, processing a second surface of the supporting substrate, opposite to the first surface, to shape the semiconductor substrate into a thin film. After shaping the semiconductor substrate into a thin film, polishing a part of the bonding layer formed at a beveled portion of the supporting substrate or the semiconductor substrate with a first polishing plane to remove the part of the bonding layera A33fter polishing the part of the bonding layer, polishing a remaining part of the bonding layer formed at the beveled portion of the supporting substrate or the semiconductor substrate with a second polishing plane different from the first polishing plane to remove the remaining part of the bonding layer.Type: GrantFiled: February 11, 2019Date of Patent: October 27, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takashi Shirono, Eiji Takano, Gen Toyota, Eiichi Shin
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Patent number: 10804152Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes: bonding a first surface of a device substrate on which a device is formed on a first surface to a support substrate via an adhesive; after bonding the device substrate to the support substrate, grinding and thinning a second surface side opposite to the first surface of the device substrate based on an in-plane processing rate at the time of forming a semiconductor substrate by RIE; after thinning the device substrate, forming a hole penetrating the device substrate by RIE; and burying metal in the hole to forma through electrode.Type: GrantFiled: February 11, 2019Date of Patent: October 13, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masaya Shima, Ippei Kume, Eiichi Shin, Eiji Takano, Takashi Shirono, Mika Fujii
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Publication number: 20190362980Abstract: A method for manufacturing a semiconductor device includes bonding a supporting substrate and a first surface of a semiconductor substrate via a bonding layer, processing a second surface of the supporting substrate, opposite to the first surface, to shape the semiconductor substrate into a thin film. After shaping the semiconductor substrate into a thin film, polishing a part of the bonding layer formed at a beveled portion of the supporting substrate or the semiconductor substrate with a first polishing plane to remove the part of the bonding layera A33fter polishing the part of the bonding layer, polishing a remaining part of the bonding layer formed at the beveled portion of the supporting substrate or the semiconductor substrate with a second polishing plane different from the first polishing plane to remove the remaining part of the bonding layer.Type: ApplicationFiled: February 11, 2019Publication date: November 28, 2019Applicant: Toshiba Memory CorporationInventors: Takashi SHIRONO, Eiji TAKANO, Gen TOYOTA, Eiichi SHIN
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Publication number: 20190348324Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes: bonding a first surface of a device substrate on which a device is formed on a first surface to a support substrate via an adhesive; after bonding the device substrate to the support substrate, grinding and thinning a second surface side opposite to the first surface of the device substrate based on an in-plane processing rate at the time of forming a semiconductor substrate by RIE; after thinning the device substrate, forming a hole penetrating the device substrate by RIE; and burying metal in the hole to forma through electrode.Type: ApplicationFiled: February 11, 2019Publication date: November 14, 2019Applicant: Toshiba Memory CorporationInventors: Masaya SHIMA, Ippei KUME, Eiichi SHIN, Eiji TAKANO, Takashi SHIRONO, Mika FUJII
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Patent number: 10068775Abstract: According to one embodiment, a method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device includes three steps of a providing step, a bonding step, and a thinning step. In the providing step, a mitigation layer that mitigates warping of the device substrate being thinned by grinding is provided on the supporting substrate. In the bonding step, the device substrate is bonded to the supporting substrate on which the mitigation layer is provided. In the thinning step, the device substrate supported by the supporting substrate is thinned by grinding.Type: GrantFiled: August 10, 2016Date of Patent: September 4, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Mika Fujii, Kazuyuki Higashi, Kazumichi Tsumura, Takashi Shirono
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Publication number: 20170076969Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming an overhanging portion in a perimeter region of a front surface side of a wafer provided with a semiconductor element on the front surface thereof by removing a portion of the wafer in perimeter region of the wafer from the front surface side of the wafer, bonding the front surface of the wafer to a supporting substrate, and thinning the wafer to less than 200 ?m in thickness by grinding the wafer from a rear surface side thereof.Type: ApplicationFiled: August 10, 2016Publication date: March 16, 2017Inventors: Takashi SHIRONO, Mika FUJII, Kazuyuki HIGASHI
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Publication number: 20170069503Abstract: According to one embodiment, a method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device includes three steps of a providing step, a bonding step, and a thinning step. In the providing step, a mitigation layer that mitigates warping of the device substrate being thinned by grinding is provided on the supporting substrate. In the bonding step, the device substrate is bonded to the supporting substrate on which the mitigation layer is provided. In the thinning step, the device substrate supported by the supporting substrate is thinned by grinding.Type: ApplicationFiled: August 10, 2016Publication date: March 9, 2017Inventors: Mika FUJII, Kazuyuki HIGASHI, Kazumichi TSUMURA, Takashi SHIRONO
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Patent number: 9123717Abstract: According to one embodiment, a semiconductor device manufacturing method includes: bonding a first wafer and a second wafer to each other, to form a stack; rubbing a film attached with a fill material in a thin-film shape into a gap located between a bevel of the first wafer and a bevel of the second wafer, to fill the gap with the fill material; and thinning the first wafer.Type: GrantFiled: July 30, 2013Date of Patent: September 1, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kenro Nakamura, Mitsuyoshi Endo, Kazuyuki Higashi, Takashi Shirono
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Publication number: 20150054172Abstract: According to one embodiment, a semiconductor device includes an integrated circuit and a conductive material. The integrated circuit is provided on a surface of a semiconductor layer. The conductive material is embedded into a via which penetrates the semiconductor layer in a thickness direction thereof and is electrically connected to the integrated circuit. The conductive material includes a contact portion and a through portion, and the contact portion includes a cross-sectional area that is greater than a cross-sectional area of the through portion.Type: ApplicationFiled: March 2, 2014Publication date: February 26, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takashi SHIRONO, Kazuyuki HIGASHI, Shinya WATANABE, Tatsuo MIGITA
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Publication number: 20140242779Abstract: According to one embodiment, a semiconductor device manufacturing method includes: bonding a first wafer and a second wafer to each other, to form a stack; rubbing a film attached with a fill material in a thin-film shape into a gap located between a bevel of the first wafer and a bevel of the second wafer, to fill the gap with the fill material; and thinning the first wafer.Type: ApplicationFiled: July 30, 2013Publication date: August 28, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kenro NAKAMURA, Mitsuyoshi ENDO, Kazuyuki HIGASHI, Takashi SHIRONO
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Patent number: 8778778Abstract: According to an embodiment, an active layer is formed on a first surface of a semiconductor substrate, a wiring layer is formed on the active layer, and an insulating layer is formed covering the wiring layer. The first surface of the semiconductor substrate is bonded to a support substrate via the insulating layer, and the semiconductor substrate bonded to the support substrate is thinned leaving the semiconductor substrate having a predetermined thickness which covers the active layer from a second surface. At least a part of area of the thinned semiconductor substrate is removed to expose the active layer.Type: GrantFiled: August 18, 2011Date of Patent: July 15, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kazumasa Tanida, Masahiro Sekiguchi, Masayuki Dohi, Tsuyoshi Matsumura, Hideo Numata, Mari Otsuka, Naoko Yamaguchi, Takashi Shirono, Satoshi Hongo
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Patent number: 8748316Abstract: According to an embodiment, a method of manufacturing a semiconductor device includes polishing a peripheral portion of the semiconductor substrate, and forming a protective film to be an insulating film, on a surface of the semiconductor substrate including a surface exposed by the polishing.Type: GrantFiled: June 27, 2011Date of Patent: June 10, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Shirono, Mie Matsuo, Hideo Numata, Kazumasa Tanida, Tsuyoshi Matsumura
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Patent number: 8609511Abstract: According to one embodiment, an insulation film is formed over the surface, backside, and sides of a first substrate. Next, the insulation film formed over the surface of the first substrate is removed. Then, a joining layer is formed over the surface of the first substrate, from which the insulation film has been removed. Subsequently, the first substrate is bonded to a second substrate via a joining layer.Type: GrantFiled: August 29, 2011Date of Patent: December 17, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Shirono, Kazumasa Tanida, Naoko Yamaguchi, Satoshi Hongo, Tsuyoshi Matsumura
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Publication number: 20120068290Abstract: According to one embodiment, an insulation film is formed over the surface, backside, and sides of a first substrate. Next, the insulation film formed over the surface of the first substrate is removed. Then, a joining layer is formed over the surface of the first substrate, from which the insulation film has been removed. Subsequently, the first substrate is bonded to a second substrate via a joining layer.Type: ApplicationFiled: August 29, 2011Publication date: March 22, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Takashi Shirono, Kazumasa Tanida, Naoko Yamaguchi, Satoshi Hongo, Tsuyoshi Matsumura
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Publication number: 20120049312Abstract: According to an embodiment, an active layer is formed on a first surface of a semiconductor substrate, a wiring layer is formed on the active layer, and an insulating layer is formed covering the wiring layer. The first surface of the semiconductor substrate is bonded to a support substrate via the insulating layer, and the semiconductor substrate bonded to the support substrate is thinned leaving the semiconductor substrate having a predetermined thickness which covers the active layer from a second surface. At least a part of area of the thinned semiconductor substrate is removed to expose the active layer.Type: ApplicationFiled: August 18, 2011Publication date: March 1, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazumasa TANIDA, Masahiro Sekiguchi, Masayuki Dohi, Tsuyoshi Matsumura, Hideo Numata, Mari Otsuka, Naoko Yamaguchi, Takashi Shirono, Satoshi Hongo
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Publication number: 20110317050Abstract: According to an embodiment, a method of manufacturing a semiconductor device includes polishing a peripheral portion of the semiconductor substrate, and forming a protective film to be an insulating film, on a surface of the semiconductor substrate including a surface exposed by the polishing.Type: ApplicationFiled: June 27, 2011Publication date: December 29, 2011Inventors: Takashi Shirono, Mie Matsuo, Hideo Numata, Kazumasa Tanida, Tsuyoshi Matsumura