Patents by Inventor Takashi Shuto
Takashi Shuto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10811659Abstract: An object is to provide a separator excellent in adhesiveness to electrodes and a separator for an electricity storage device also excellent in handling performance. A separator for an electricity storage device having a polyolefin microporous film and a thermoplastic polymer coating layer covering at least a part of at least one of surfaces of the polyolefin microporous film, in which the thermoplastic polymer coating layer, on the polyolefin microporous film, has a portion containing a thermoplastic polymer and a portion not containing the thermoplastic polymer in a sea-island configuration, the thermoplastic polymer coating layer contains the thermoplastic polymer having at least two glass-transition temperatures, at least one of the glass-transition temperatures is in a range of less than 20° C. and at least one of the glass-transition temperatures is in a range of 20° C. or more.Type: GrantFiled: November 2, 2018Date of Patent: October 20, 2020Assignee: Asahi Kasei E-materials CorporationInventors: Hiroshi Miyazawa, Keitaro Ameyama, Takashi Shuto
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Patent number: 10522483Abstract: Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations.Type: GrantFiled: April 10, 2019Date of Patent: December 31, 2019Assignee: Intel CorporationInventor: Takashi Shuto
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Publication number: 20190237413Abstract: Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations.Type: ApplicationFiled: April 10, 2019Publication date: August 1, 2019Inventor: Takashi Shuto
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Patent number: 10304785Abstract: Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations.Type: GrantFiled: June 19, 2018Date of Patent: May 28, 2019Assignee: Intel CorporationInventor: Takashi Shuto
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Publication number: 20190140242Abstract: An object is to provide a separator excellent in adhesiveness to electrodes and a separator for an electricity storage device also excellent in handling performance. A separator for an electricity storage device having a polyolefin microporous film and a thermoplastic polymer coating layer covering at least a part of at least one of surfaces of the polyolefin microporous film, in which the thermoplastic polymer coating layer, on the polyolefin microporous film, has a portion containing a thermoplastic polymer and a portion not containing the thermoplastic polymer in a sea-island configuration, the thermoplastic polymer coating layer contains the thermoplastic polymer having at least two glass-transition temperatures, at least one of the glass-transition temperatures is in a range of less than 20° C. and at least one of the glass-transition temperatures is in a range of 20° C. or more.Type: ApplicationFiled: November 2, 2018Publication date: May 9, 2019Applicant: Asahi Kasei E-materials CorporationInventors: Hiroshi Miyazawa, Keitaro Ameyama, Takashi Shuto
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Patent number: 10153473Abstract: An object is to provide a separator excellent in adhesiveness to electrodes and a separator for an electricity storage device also excellent in handling performance. A separator for an electricity storage device having a polyolefin microporous film and a thermoplastic polymer coating layer covering at least a part of at least one of surfaces of the polyolefin microporous film, in which the thermoplastic polymer coating layer, on the polyolefin microporous film, has a portion containing a thermoplastic polymer and a portion not containing the thermoplastic polymer in a sea-island configuration, the thermoplastic polymer coating layer contains the thermoplastic polymer having at least two glass-transition temperatures, at least one of the glass-transition temperatures is in a range of less than 20° C. and at least one of the glass-transition temperatures is in a range of 20° C. or more.Type: GrantFiled: July 26, 2013Date of Patent: December 11, 2018Assignee: Asahi Kasei E-materials CorporationInventors: Hiroshi Miyazawa, Keitaro Ameyama, Takashi Shuto
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Publication number: 20180308805Abstract: Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations.Type: ApplicationFiled: June 19, 2018Publication date: October 25, 2018Inventor: Takashi Shuto
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Patent number: 10014263Abstract: Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations.Type: GrantFiled: June 1, 2017Date of Patent: July 3, 2018Assignee: Intel CorporationInventor: Takashi Shuto
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Patent number: 9887110Abstract: A method including clamping an integrated circuit package substrate between first and second supporting substrates; exposing the clamped package substrate to a heat source from a single direction; and modifying a shape of the package substrate. An apparatus including a first and second supporting substrates, the first supporting substrate including a two-dimensional area that is 75 percent to 95 percent of the area of the first side of the package substrate and the second supporting substrate including a two-dimensional area that is at least equivalent to the area of a package substrate and each of the first supporting substrate and the second supporting substrate include a body having a cavity therein such that when assembled on opposite sides of a package substrate, each cavity has a volume dimension such that the body of the supporting substrate is not in contact with an area of a package substrate.Type: GrantFiled: September 27, 2014Date of Patent: February 6, 2018Assignee: Intel CorporationInventors: Chee Key Chung, Takashi Shuto
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Publication number: 20170271277Abstract: Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations.Type: ApplicationFiled: June 1, 2017Publication date: September 21, 2017Inventor: Takashi Shuto
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Patent number: 9685414Abstract: Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations.Type: GrantFiled: June 26, 2013Date of Patent: June 20, 2017Assignee: Intel CorporationInventor: Takashi Shuto
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Publication number: 20160268149Abstract: A method including clamping an integrated circuit package substrate between first and second supporting substrates; exposing the clamped package substrate to a heat source from a single direction; and modifying a shape of the package substrate. An apparatus including a first and second supporting substrates, the first supporting substrate including a two-dimensional area that is 75 percent to 95 percent of the area of the first side of the package substrate and the second supporting substrate including a two-dimensional area that is at least equivalent to the area of a package substrate and each of the first supporting substrate and the second supporting substrate include a body having a cavity therein such that when assembled on opposite sides of a package substrate, each cavity has a volume dimension such that the body of the supporting substrate is not in contact with an area of a package substrate.Type: ApplicationFiled: September 27, 2014Publication date: September 15, 2016Inventors: Chee Key CHUNG, Takashi SHUTO
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Publication number: 20150188108Abstract: An object is to provide a separator excellent in adhesiveness to electrodes and a separator for an electricity storage device also excellent in handling performance. A separator for an electricity storage device having a polyolefin microporous film and a thermoplastic polymer coating layer covering at least a part of at least one of surfaces of the polyolefin microporous film, in which the thermoplastic polymer coating layer, on the polyolefin microporous film, has a portion containing a thermoplastic polymer and a portion not containing the thermoplastic polymer in a sea-island configuration, the thermoplastic polymer coating layer contains the thermoplastic polymer having at least two glass-transition temperatures, at least one of the glass-transition temperatures is in a range of less than 20° C. and at least one of the glass-transition temperatures is in a range of 20° C. or more.Type: ApplicationFiled: July 26, 2013Publication date: July 2, 2015Applicant: ASAHI KASEI E-MATERIALS CORPORATIONInventors: Hiroshi Miyazawa, Keitaro Ameyama, Takashi Shuto
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Publication number: 20150001731Abstract: Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations.Type: ApplicationFiled: June 26, 2013Publication date: January 1, 2015Inventor: Takashi Shuto
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Patent number: 7935891Abstract: The present invention relates to a method of manufacturing a wiring board comprising: a build-up layer, in which wiring patterns are piled with insulating layers; and a core substrate, which is separately formed from the build-up layer, the method comprising the steps of: separably forming the build-up layer on a plate-shaped support; electrically connecting the core substrate to the wiring patterns of the build-up layer on the support; and removing the support from the build-up layer so as to form the wiring board, in which the build-up layer is connected to the core substrate. By separably forming the build-up layer and the core substrate, the wiring board effectively exhibiting characteristics thereof can be produced.Type: GrantFiled: February 14, 2008Date of Patent: May 3, 2011Assignee: Fujitsu LimitedInventors: Takashi Shuto, Kenji Takano, Kenji Iida, Kenichiro Abe, Keiji Arai, Kiyotaka Seyama
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Publication number: 20080142256Abstract: The present invention relates to a method of manufacturing a wiring board comprising: a build-up layer, in which wiring patterns are piled with insulating layers; and a core substrate, which is separately formed from the build-up layer, the method comprising the steps of: separably forming the build-up layer on a plate-shaped support; electrically connecting the core substrate to the wiring patterns of the build-up layer on the support; and removing the support from the build-up layer so as to form the wiring board, in which the build-up layer is connected to the core substrate. By separably forming the build-up layer and the core substrate, the wiring board effectively exhibiting characteristics thereof can be produced.Type: ApplicationFiled: February 14, 2008Publication date: June 19, 2008Applicant: FUJITSU LIMITEDInventors: Takashi Shuto, Kenji Takano, Kenji Iida, Kenichiro Abe, Keiji Arai, Kiyotaka Seyama
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Patent number: 7377030Abstract: The present invention relates to a method of manufacturing a wiring board comprising: a build-up layer, in which wiring patterns are piled with insulating layers; and a core substrate, which is separately formed from the build-up layer, the method comprising the steps of: separably forming the build-up layer on a plate-shaped support; electrically connecting the core substrate to the wiring patterns of the build-up layer on the support; and removing the support from the build-up layer so as to form the wiring board, in which the build-up layer is connected to the core substrate. By separably forming the build-up layer and the core substrate, the wiring board effectively exhibiting characteristics thereof can be produced.Type: GrantFiled: November 4, 2005Date of Patent: May 27, 2008Assignee: Fujitsu LimitedInventors: Takashi Shuto, Kenji Takano, Kenji Ilda, Kenichiro Abe, Keiji Arai, Kiyotaka Seyama
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Patent number: 7152314Abstract: The method of manufacturing a circuit board is capable of preventing deformation of a core substrate, ensuring size thereof and highly concentrating cable patterns so as to realize compact and high-performance semiconductor devices. The method of manufacturing a circuit board of the present invention comprises the steps of: forming a multilayered body, in which cable patterns on different layers insulated by an insulating layer are electrically connected, on a core substrate by a buildup process; and separating the multilayered body from the core substrate. A metal layer is vacuum-adhered on the core substrate.Type: GrantFiled: January 28, 2004Date of Patent: December 26, 2006Assignee: Fujitsu LimitedInventors: Takashi Shuto, Takefumi Kashiwa, Kenji Takano, Kenji Iida, Kenichiro Abe
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Publication number: 20060112544Abstract: The present invention relates to a method of manufacturing a wiring board comprising: a build-up layer, in which wiring patterns are piled with insulating layers; and a core substrate, which is separately formed from the build-up layer, the method comprising the steps of: separably forming the build-up layer on a plate-shaped support; electrically connecting the core substrate to the wiring patterns of the build-up layer on the support; and removing the support from the build-up layer so as to form the wiring board, in which the build-up layer is connected to the core substrate. By separably forming the build-up layer and the core substrate, the wiring board effectively exhibiting characteristics thereof can be produced.Type: ApplicationFiled: November 4, 2005Publication date: June 1, 2006Applicant: FUJITSU LIMITEDInventors: Takashi Shuto, Kenji Takano, Kenji IIda, Kenichiro Abe, Keiji Arai, Kiyotaka Seyama
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Patent number: 7002080Abstract: A multilayer wiring board is composed of a core portion, a first wiring portion and a second wiring portion. The core portion includes a core insulating layer containing a carbon fiber material. The first wiring portion is bonded to the core portion and has a laminated structure including at least a first insulating layer and a first wiring pattern, the first insulating layer containing glass cloth. The second wiring portion is bonded to the first wiring portion and has a laminated structure including at least a second insulating layer and a second wiring pattern. The core portion, the first wiring portion and the second wiring portion are arranged in a stack.Type: GrantFiled: July 30, 2003Date of Patent: February 21, 2006Assignee: Fujitsu LimitedInventors: Motoaki Tani, Nobuyuki Hayashi, Tomoyuki Abe, Yasuhito Takahashi, Takashi Shuto