Patents by Inventor Takashi Shuto

Takashi Shuto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10811659
    Abstract: An object is to provide a separator excellent in adhesiveness to electrodes and a separator for an electricity storage device also excellent in handling performance. A separator for an electricity storage device having a polyolefin microporous film and a thermoplastic polymer coating layer covering at least a part of at least one of surfaces of the polyolefin microporous film, in which the thermoplastic polymer coating layer, on the polyolefin microporous film, has a portion containing a thermoplastic polymer and a portion not containing the thermoplastic polymer in a sea-island configuration, the thermoplastic polymer coating layer contains the thermoplastic polymer having at least two glass-transition temperatures, at least one of the glass-transition temperatures is in a range of less than 20° C. and at least one of the glass-transition temperatures is in a range of 20° C. or more.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: October 20, 2020
    Assignee: Asahi Kasei E-materials Corporation
    Inventors: Hiroshi Miyazawa, Keitaro Ameyama, Takashi Shuto
  • Patent number: 10522483
    Abstract: Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: December 31, 2019
    Assignee: Intel Corporation
    Inventor: Takashi Shuto
  • Publication number: 20190237413
    Abstract: Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations.
    Type: Application
    Filed: April 10, 2019
    Publication date: August 1, 2019
    Inventor: Takashi Shuto
  • Patent number: 10304785
    Abstract: Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventor: Takashi Shuto
  • Publication number: 20190140242
    Abstract: An object is to provide a separator excellent in adhesiveness to electrodes and a separator for an electricity storage device also excellent in handling performance. A separator for an electricity storage device having a polyolefin microporous film and a thermoplastic polymer coating layer covering at least a part of at least one of surfaces of the polyolefin microporous film, in which the thermoplastic polymer coating layer, on the polyolefin microporous film, has a portion containing a thermoplastic polymer and a portion not containing the thermoplastic polymer in a sea-island configuration, the thermoplastic polymer coating layer contains the thermoplastic polymer having at least two glass-transition temperatures, at least one of the glass-transition temperatures is in a range of less than 20° C. and at least one of the glass-transition temperatures is in a range of 20° C. or more.
    Type: Application
    Filed: November 2, 2018
    Publication date: May 9, 2019
    Applicant: Asahi Kasei E-materials Corporation
    Inventors: Hiroshi Miyazawa, Keitaro Ameyama, Takashi Shuto
  • Patent number: 10153473
    Abstract: An object is to provide a separator excellent in adhesiveness to electrodes and a separator for an electricity storage device also excellent in handling performance. A separator for an electricity storage device having a polyolefin microporous film and a thermoplastic polymer coating layer covering at least a part of at least one of surfaces of the polyolefin microporous film, in which the thermoplastic polymer coating layer, on the polyolefin microporous film, has a portion containing a thermoplastic polymer and a portion not containing the thermoplastic polymer in a sea-island configuration, the thermoplastic polymer coating layer contains the thermoplastic polymer having at least two glass-transition temperatures, at least one of the glass-transition temperatures is in a range of less than 20° C. and at least one of the glass-transition temperatures is in a range of 20° C. or more.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: December 11, 2018
    Assignee: Asahi Kasei E-materials Corporation
    Inventors: Hiroshi Miyazawa, Keitaro Ameyama, Takashi Shuto
  • Publication number: 20180308805
    Abstract: Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations.
    Type: Application
    Filed: June 19, 2018
    Publication date: October 25, 2018
    Inventor: Takashi Shuto
  • Patent number: 10014263
    Abstract: Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: July 3, 2018
    Assignee: Intel Corporation
    Inventor: Takashi Shuto
  • Patent number: 9887110
    Abstract: A method including clamping an integrated circuit package substrate between first and second supporting substrates; exposing the clamped package substrate to a heat source from a single direction; and modifying a shape of the package substrate. An apparatus including a first and second supporting substrates, the first supporting substrate including a two-dimensional area that is 75 percent to 95 percent of the area of the first side of the package substrate and the second supporting substrate including a two-dimensional area that is at least equivalent to the area of a package substrate and each of the first supporting substrate and the second supporting substrate include a body having a cavity therein such that when assembled on opposite sides of a package substrate, each cavity has a volume dimension such that the body of the supporting substrate is not in contact with an area of a package substrate.
    Type: Grant
    Filed: September 27, 2014
    Date of Patent: February 6, 2018
    Assignee: Intel Corporation
    Inventors: Chee Key Chung, Takashi Shuto
  • Publication number: 20170271277
    Abstract: Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations.
    Type: Application
    Filed: June 1, 2017
    Publication date: September 21, 2017
    Inventor: Takashi Shuto
  • Patent number: 9685414
    Abstract: Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: June 20, 2017
    Assignee: Intel Corporation
    Inventor: Takashi Shuto
  • Publication number: 20160268149
    Abstract: A method including clamping an integrated circuit package substrate between first and second supporting substrates; exposing the clamped package substrate to a heat source from a single direction; and modifying a shape of the package substrate. An apparatus including a first and second supporting substrates, the first supporting substrate including a two-dimensional area that is 75 percent to 95 percent of the area of the first side of the package substrate and the second supporting substrate including a two-dimensional area that is at least equivalent to the area of a package substrate and each of the first supporting substrate and the second supporting substrate include a body having a cavity therein such that when assembled on opposite sides of a package substrate, each cavity has a volume dimension such that the body of the supporting substrate is not in contact with an area of a package substrate.
    Type: Application
    Filed: September 27, 2014
    Publication date: September 15, 2016
    Inventors: Chee Key CHUNG, Takashi SHUTO
  • Publication number: 20150188108
    Abstract: An object is to provide a separator excellent in adhesiveness to electrodes and a separator for an electricity storage device also excellent in handling performance. A separator for an electricity storage device having a polyolefin microporous film and a thermoplastic polymer coating layer covering at least a part of at least one of surfaces of the polyolefin microporous film, in which the thermoplastic polymer coating layer, on the polyolefin microporous film, has a portion containing a thermoplastic polymer and a portion not containing the thermoplastic polymer in a sea-island configuration, the thermoplastic polymer coating layer contains the thermoplastic polymer having at least two glass-transition temperatures, at least one of the glass-transition temperatures is in a range of less than 20° C. and at least one of the glass-transition temperatures is in a range of 20° C. or more.
    Type: Application
    Filed: July 26, 2013
    Publication date: July 2, 2015
    Applicant: ASAHI KASEI E-MATERIALS CORPORATION
    Inventors: Hiroshi Miyazawa, Keitaro Ameyama, Takashi Shuto
  • Publication number: 20150001731
    Abstract: Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations.
    Type: Application
    Filed: June 26, 2013
    Publication date: January 1, 2015
    Inventor: Takashi Shuto
  • Patent number: 7935891
    Abstract: The present invention relates to a method of manufacturing a wiring board comprising: a build-up layer, in which wiring patterns are piled with insulating layers; and a core substrate, which is separately formed from the build-up layer, the method comprising the steps of: separably forming the build-up layer on a plate-shaped support; electrically connecting the core substrate to the wiring patterns of the build-up layer on the support; and removing the support from the build-up layer so as to form the wiring board, in which the build-up layer is connected to the core substrate. By separably forming the build-up layer and the core substrate, the wiring board effectively exhibiting characteristics thereof can be produced.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: May 3, 2011
    Assignee: Fujitsu Limited
    Inventors: Takashi Shuto, Kenji Takano, Kenji Iida, Kenichiro Abe, Keiji Arai, Kiyotaka Seyama
  • Publication number: 20080142256
    Abstract: The present invention relates to a method of manufacturing a wiring board comprising: a build-up layer, in which wiring patterns are piled with insulating layers; and a core substrate, which is separately formed from the build-up layer, the method comprising the steps of: separably forming the build-up layer on a plate-shaped support; electrically connecting the core substrate to the wiring patterns of the build-up layer on the support; and removing the support from the build-up layer so as to form the wiring board, in which the build-up layer is connected to the core substrate. By separably forming the build-up layer and the core substrate, the wiring board effectively exhibiting characteristics thereof can be produced.
    Type: Application
    Filed: February 14, 2008
    Publication date: June 19, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Takashi Shuto, Kenji Takano, Kenji Iida, Kenichiro Abe, Keiji Arai, Kiyotaka Seyama
  • Patent number: 7377030
    Abstract: The present invention relates to a method of manufacturing a wiring board comprising: a build-up layer, in which wiring patterns are piled with insulating layers; and a core substrate, which is separately formed from the build-up layer, the method comprising the steps of: separably forming the build-up layer on a plate-shaped support; electrically connecting the core substrate to the wiring patterns of the build-up layer on the support; and removing the support from the build-up layer so as to form the wiring board, in which the build-up layer is connected to the core substrate. By separably forming the build-up layer and the core substrate, the wiring board effectively exhibiting characteristics thereof can be produced.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: May 27, 2008
    Assignee: Fujitsu Limited
    Inventors: Takashi Shuto, Kenji Takano, Kenji Ilda, Kenichiro Abe, Keiji Arai, Kiyotaka Seyama
  • Patent number: 7152314
    Abstract: The method of manufacturing a circuit board is capable of preventing deformation of a core substrate, ensuring size thereof and highly concentrating cable patterns so as to realize compact and high-performance semiconductor devices. The method of manufacturing a circuit board of the present invention comprises the steps of: forming a multilayered body, in which cable patterns on different layers insulated by an insulating layer are electrically connected, on a core substrate by a buildup process; and separating the multilayered body from the core substrate. A metal layer is vacuum-adhered on the core substrate.
    Type: Grant
    Filed: January 28, 2004
    Date of Patent: December 26, 2006
    Assignee: Fujitsu Limited
    Inventors: Takashi Shuto, Takefumi Kashiwa, Kenji Takano, Kenji Iida, Kenichiro Abe
  • Publication number: 20060112544
    Abstract: The present invention relates to a method of manufacturing a wiring board comprising: a build-up layer, in which wiring patterns are piled with insulating layers; and a core substrate, which is separately formed from the build-up layer, the method comprising the steps of: separably forming the build-up layer on a plate-shaped support; electrically connecting the core substrate to the wiring patterns of the build-up layer on the support; and removing the support from the build-up layer so as to form the wiring board, in which the build-up layer is connected to the core substrate. By separably forming the build-up layer and the core substrate, the wiring board effectively exhibiting characteristics thereof can be produced.
    Type: Application
    Filed: November 4, 2005
    Publication date: June 1, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Takashi Shuto, Kenji Takano, Kenji IIda, Kenichiro Abe, Keiji Arai, Kiyotaka Seyama
  • Patent number: 7002080
    Abstract: A multilayer wiring board is composed of a core portion, a first wiring portion and a second wiring portion. The core portion includes a core insulating layer containing a carbon fiber material. The first wiring portion is bonded to the core portion and has a laminated structure including at least a first insulating layer and a first wiring pattern, the first insulating layer containing glass cloth. The second wiring portion is bonded to the first wiring portion and has a laminated structure including at least a second insulating layer and a second wiring pattern. The core portion, the first wiring portion and the second wiring portion are arranged in a stack.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: February 21, 2006
    Assignee: Fujitsu Limited
    Inventors: Motoaki Tani, Nobuyuki Hayashi, Tomoyuki Abe, Yasuhito Takahashi, Takashi Shuto