Abstract: To more reliably supply cooling water to a reactor pressure vessel and a reactor containment vessel using a back-up building if a severe accident should occur, a boiling water type nuclear power plant includes a nuclear reactor building including a reactor containment vessel, and an external building, which is installed independently outside the nuclear reactor building and which has an anti-hazard property. The external building has a power source and an operating panel independent of the nuclear reactor building. The boiling water type nuclear power plant includes a water injection pump installed inside the external building, an alternative water injection pipe performing water injection at least on a reactor pressure vessel or the reactor containment vessel in the nuclear reactor building from the water injection pump, and a valve connected to the alternative water injection pipe, making it possible to perform alternative water injection if a severe accident occurs.

Abstract: To more reliably supply cooling water to a reactor pressure vessel and a reactor containment vessel using a back-up building if a severe accident should occur, a boiling water type nuclear power plant includes a nuclear reactor building including a reactor containment vessel, and an external building, which is installed independently outside the nuclear reactor building and which has an anti-hazard property. The external building has a power source and an operating panel independent of the nuclear reactor building. The boiling water type nuclear power plant includes a water injection pump installed inside the external building, an alternative water injection pipe performing water injection at least on a reactor pressure vessel or the reactor containment vessel in the nuclear reactor building from the water injection pump, and a valve connected to the alternative water injection pipe, making it possible to perform alternative water injection if a severe accident occurs.

Abstract: In a standard cell, dummy transistors have p-type and n-type dummy gate electrodes. The dummy transistors are in an OFF state all the time. The gate length of each of the dummy gate electrodes is extended over an end portion of a diffusion region toward the inside of the standard cell. Thus, the total surface area and the total perimeter of respective gate electrodes of all transistors provided in the standard cell are increased. As a result, for example, even though shapes of gate electrodes of transistors vary between the standard cell and each of other standard cells, transistor characteristics are substantially equal among the standard cells. Therefore, variations in delays of signals generated between the standard cells can be suppressed.

Abstract: An integrated circuit timing analysis system includes: a first storage section for storing a layout of an integrated circuit including a plurality of transistors; and a processing section for processing the layout stored in the first storage section. The processing section includes a layout dividing section for dividing the layout stored in the first storage section into a plurality of sublayouts, a timing analysis section for performing statistical timing analysis on each of the sublayouts and a data compilation section for compiling the analysis data of the sublayouts to determine a timing of the integrated circuit.

Abstract: A simulation device for an integrated circuit according to the present invention comprises a first memory unit, a first input unit, a second memory unit, an execute unit, a second input unit and an output unit. A net list of a particular path in inter-cell paths in the integrated circuit comprising a plurality of synchronizing circuit cells is stored in the first memory unit. The first input unit appends a variation information relating to gate lengths, gate widths and the like of transistors to the net list stored in the first memory unit. The variation net list to which the variation information is appended by the first input unit is stored in the second memory unit. The execute unit executes a simulation using the variation net list stored in the second memory unit to thereby calculate a delay variation distribution. The second input unit appends a circuit information to the path.

Abstract: From a trend for performance correlation coefficients (M1, M2) between circuits of the same type and of different process generations, a performance correlation coefficient M between a current generation circuit and a next generation circuit is predicted, and from a trend for performance correlation coefficients (R1, R2, R3) between circuits of the same process generation and of different types, a performance correlation coefficient R between different types of circuits in accordance with a next generation process is predicted. Thus, based on known performance of a circuit A, performances of a next generation circuits AA and BB are predicted using the predicted performance correlation coefficients M and R.

Abstract: In a standard cell, dummy transistors have p-type and n-type dummy gate electrodes. The dummy transistors are in an OFF state all the time. The gate length of each of the dummy gate electrodes is extended over an end portion of a diffusion region toward the inside of the standard cell. Thus, the total surface area and the total perimeter of respective gate electrodes of all transistors provided in the standard cell are increased. As a result, for example, even though shapes of gate electrodes of transistors vary between the standard cell and each of other standard cells, transistor characteristics are substantially equal among the standard cells. Therefore, variations in delays of signals generated between the standard cells can be suppressed.

Abstract: From a trend for performance correlation coefficients (M1, M2) between circuits of the same type and of different process generations, a performance correlation coefficient M between a current generation circuit and a next generation circuit is predicted, and from a trend for performance correlation coefficients (R1, R2, R3) between circuits of the same process generation and of different types, a performance correlation coefficient R between different types of circuits in accordance with a next generation process is predicted. Thus, based on known performance of a circuit A, performances of a next generation circuits AA and BB are predicted using the predicted performance correlation coefficients M and R.