Abstract: A method for verifying layout interconnections includes extracting a loop circuit as a loop portion in a first circuit model. The first circuit model includes first branch interconnections included in the loop portion and second branch interconnections, first nodes, and terminals of circuit elements. The loop portion is replaced with a second node to generate a second circuit model which does not have a loop portion, based on the first circuit model. A second current value of each of the second branch interconnections is calculated, based on the second circuit model. A third circuit model of the loop portion is generated, based on the first interconnections. A first current value of each of the first branch interconnections is calculated, based on the third circuit model. The first and second current value are compared with a predetermined current value to carry out verification.

Abstract: A method for verifying layout interconnections includes steps of (a) to (f). The step (a) extracts a loop circuit as a loop portion in a first circuit model. The first circuit model includes: branch interconnections which includes first branch interconnections included in the loop portion and other branch interconnections as second branch interconnections, first nodes, each of which is connected with an edge of corresponding one of the branch interconnections, and terminals of circuit elements, each of which is connected with an edge of corresponding one of the branch interconnections. The step (b) replacs the loop portion with a second node to generate a second circuit model which does not have a loop portion, based on the first circuit model. The step (c) calculats a second current value of each of the second branch interconnections, based on the second circuit model. The Sept (d) generates a third circuit model of the loop portion, based on the first interconnections.

Abstract: A method includes the steps of estimating a positive-component average current avg_p and a negative-component average current avg_n of each of terminals of circuit elements; separating the terminals into a positive-node terminal set and a negative-node terminal set by a target branch; calculating Iavg_p and Iavg_n of the target branch as follows: Iavg_p = min ? ( ? m = 1 M ? ? ? a m · avg_n m , ? m = 1 M ? ( 1 - ? ? a m ) · avg_p m , ) , and Iavg_n = min ? ( ? m = 1 M ? ? ? a m · avg_p m , ? m = 1 M ? ( 1 - ? ? a m ) · avg_n m , ) , wherein m is the sequential number of the terminals, M is the highest sequential number, am=1 or am=0 depending on the m-th terminal belonging to the positive-node terminal set or negative-node terminal set; selecting a larger value of Iavg_p and Iavg_n as the target branch; and determining the size of the interconnect for the target branch.

Abstract: A method includes the steps of estimating a positive-component average current avg_p and a negative-component average current avg_n of each of terminals of circuit elements; separating the terminals into a positive-node terminal set and a negative-node terminal set by a target branch; calculating Iavg_p and Iavg_n of the target branch as follows: 1 Iavg_p = min ⁡ ( ∑ m = 1 M ⁢   ⁢ a m · avg_n m , ∑ m = 1 M ⁢ ( 1 -   ⁢ a m ) · avg_p m , ) , and Iavg_n = min ⁢ ( ∑ m = 1 M ⁢   ⁢ a m · avg_p m , ∑ m = 1 M ⁢ ( 1 -   ⁢ a m ) · avg_n m , ) ,