Abstract: An semiconductor detector includes an n-type semiconductor substrate, a detection electrode formed on a first surface of the semiconductor substrate, a plurality of drift electrodes formed to surround the detection electrode and applied with a voltage causing a potential gradient in which a potential changes toward the detection electrode, a radiation incidence window provided on a second surface of the semiconductor substrate, a P-type semiconductor region formed by adding boron to a surface side on the second surface of the semiconductor substrate through the radiation incidence window, and a depleting electrode causing a reverse bias between the P-type semiconductor region formed on the second surface and an N-type semiconductor region formed in the semiconductor substrate. F is added to the P-type semiconductor region, and a region with the highest concentration of F is located deeper than a region with the highest concentration of B.

Abstract: An X-ray detector and an X-ray measurement device capable of improving detection efficiency of an X-ray while maintaining high resolution are provided. An X-ray detector includes: a first SDD chip that detects a fluorescent X-ray generated from a sample with a first energy sensitivity; a second SDD chip that detects the fluorescent X-ray with a second energy sensitivity different from the first energy sensitivity; a first signal line electrically connected to the first SDD chip; and a second signal line electrically connected to the second SDD chip. The X-ray detector further includes an amplifier that is electrically connected to the first signal line and the second signal line and amplifies a signal.

Abstract: In an optical modulator 115 of an embodiment, an optical waveguide core 121 is configured from an n? type semiconductor region 134, a gate insulating film 136 on the n? type semiconductor region 134, and a p? type semiconductor region 137 on the gate insulating film 136. Further, a width W1 of the n? type semiconductor region 134 and a width W1 of the p? type semiconductor region 137 are equally formed and are layered without being shifted. Therefore, an optical modulator having stable optical characteristics can be provided.

Abstract: Disclosed herein is a technique for realizing a high-performance and high-reliability silicon carbide semiconductor device. A trenched MISFET with a trench formed into the drift through a p-type body layer 105 includes an n-type resistance relaxation layer 109 covering the bottom portion of the trench, and a p-type field relaxation layer 108. The p-type field relaxation layer 108 is separated from the trench bottom portion via the resistance relaxation layer 109, and is wider than the resistance relaxation layer 109. This achieves a low ON resistance, high reliability, and high voltage resistance at the same time. By forming the field relaxation layer beneath the trench, feedback capacitance can be controlled to achieve a high switching rate and high reliability.

Abstract: An object of the present invention is to provide an image processing apparatus that quickly and precisely measures or evaluates a distortion in a field of view and a charged particle beam apparatus. To attain the object, an image processing apparatus or the like is proposed which acquires a first image of a first area of an imaging target and a second image of a second area that is located at a different position than the first area and partially overlaps with the first area and determines the distance between a measurement point in the second image and a second part of the second image that corresponds to a particular area for a plurality of sites in the overlapping area of the first image and the second image.

Abstract: In an optical modulator 115 of an embodiment, an optical waveguide core 121 is configured from an n? type semiconductor region 134, a gate insulating film 136 on the n? type semiconductor region 134, and a p? type semiconductor region 137 on the gate insulating film 136. Further, a width W1 of the n? type semiconductor region 134 and a width W1 of the p? type semiconductor region 137 are equally formed and are layered without being shifted. Therefore, an optical modulator having stable optical characteristics can be provided.

Abstract: In order to provide a high-performance and reliable silicon carbide semiconductor device, in a silicon carbide semiconductor device including an n-type SiC epitaxial substrate, a p-type body layer, a p-type body layer potential fixing region and a nitrogen-introduced n-type first source region formed in the p-type body layer, an n-type second source region to which phosphorus which has a solid-solubility limit higher than that of nitrogen and is easily diffused is introduced is formed inside the nitrogen-introduced n-type first source region so as to be separated from both of the p-type body layer and the p-type body layer potential fixing region.

Abstract: In order to provide a high-performance and reliable silicon carbide semiconductor device, in a silicon carbide semiconductor device including an n-type SiC epitaxial substrate, a p-type body layer, a p-type body layer potential fixing region and a nitrogen-introduced n-type first source region formed in the p-type body layer, an n-type second source region to which phosphorus which has a solid-solubility limit higher than that of nitrogen and is easily diffused is introduced is formed inside the nitrogen-introduced n-type first source region so as to be separated from both of the p-type body layer and the p-type body layer potential fixing region.

Abstract: Disclosed herein is a technique for realizing a high-performance and high-reliability silicon carbide semiconductor device. A trenched MISFET with a trench formed into the drift through a p-type body layer 105 includes an n-type resistance relaxation layer 109 covering the bottom portion of the trench, and a p-type field relaxation layer 108. The p-type field relaxation layer 108 is separated from the trench bottom portion via the resistance relaxation layer 109, and is wider than the resistance relaxation layer 109. This achieves a low ON resistance, high reliability, and high voltage resistance at the same time. By forming the field relaxation layer beneath the trench, feedback capacitance can be controlled to achieve a high switching rate and high reliability.

Abstract: The present invention provides a technique capable of realizing a silicon carbide semiconductor device having high performance and high reliability. By constituting a channel region by an n?-type, intrinsic, or p?-type channel region and a p+-type channel region, a high channel mobility and a high threshold voltage are realized. Further, by constituting a source region by an n+-type source region and an n++-type source region, and forming the n+-type source region between the p+-type channel region and the n++-type source region, an electric field in the p+-type channel region is relaxed to suppress deterioration of a gate insulating film, and also by electrically connecting a source wiring electrode to the n++-type source region, a contact resistance is decreased.

Abstract: The present invention provides a technique capable of realizing a silicon carbide semiconductor device having high performance and high reliability. By constituting a channel region by an n?-type, intrinsic, or p?-type channel region and a p+-type channel region, a high channel mobility and a high threshold voltage are realized. Further, by constituting a source region by an n+-type source region and an n++-type source region, and forming the n+-type source region between the p+-type channel region and the n++-type source region, an electric field in the p+-type channel region is relaxed to suppress deterioration of a gate insulating film, and also by electrically connecting a source wiring electrode to the n++-type source region, a contact resistance is decreased.

Abstract: An object of the present invention is to provide an image processing apparatus that quickly and precisely measures or evaluates a distortion in a field of view and a charged particle beam apparatus. To attain the object, an image processing apparatus or the like is proposed which acquires a first image of a first area of an imaging target and a second image of a second area that is located at a different position than the first area and partially overlaps with the first area and determines the distance between a measurement point in the second image and a second part of the second image that corresponds to a particular area for a plurality of sites in the overlapping area of the first image and the second image.

Abstract: Source and drain diffusion layers by an extremely shallower box shaped highly doped impurity distribution that was not obtainable so far by the existent solid phase growing is attained by liquid phase growing with no effects on the gate electrode thereby attaining low consumption power and operation at large current and higher speed in a micro-refined semiconductor device. Contact with inter-connection layer over the entire region of the source and drain diffusion layers is enabled overstriding the gate electrode and without short circuit with the gate electrode by utilizing that the etching selectivity of an insulation film comprising Al as a main constituent atom is extremely higher with respect to an Si oxide film.

Abstract: A high performance super-minituarized double gate SOIMOS being fabricated by re-distributing the impurity with high concentration at the interface of a buried gate insulative film and by aligning the double gate in a self-aligned manner and furthermore, by isolating completely the buried gate electrodes electrically from each other, in which a multi-layered SOI substrate having an amorphous or polycrystal semiconductor layer constituted by way of a buried gate insulative film to a lower portion of an SOI layer is used, ion implantation is applied to the semiconductor layer in a pattern opposite to the upper gate electrode and the buried gate is constituted in a self-alignment relation with the upper gate.

Abstract: A first object of the present invention is to provide an insulated gate field effect transistor which realizes reductions in the junction depth and the resistance of source and drain junction regions beneath a gate electrode. Another object is to provide a miniaturized complementary type insulated gate field effect transistor capable of achieving a large current and a high operation speed. In a miniaturized MOS transistor, a low concentration impurity integrated layer comprising In or Ga is provided so as to have a peak in the inside of high concentration shallow source and drain diffusion layer regions. By this arrangement, the shallow source and drain diffusion layers are attracted by the impurity integrated layer, to realize shallower junctions having a high concentration and a rectangular distribution.

Abstract: A first object of the present invention is to provide an insulated gate field effect transistor which realizes reductions in the junction depth and the resistance of source and drain junction regions beneath a gate electrode. Another object is to provide a miniaturized complementary type insulated gate field effect transistor capable of achieving a large current and a high operation speed. In a miniaturized MOS transistor, a low concentration impurity integrated layer comprising In or Ga is provided so as to have a peak in the inside of high concentration shallow source and drain diffusion layer regions. By this arrangement, the shallow source and drain diffusion layers are attracted by the impurity integrated layer, to realize shallower junctions having a high concentration and a rectangular distribution.

Abstract: Source-drain diffusion regions of a shallow junction and a stacked metal silicide film structure of a low resistance in a miniaturized MIS transistor are to be attained while ensuring high reliability. The concentration of an impurity (As, P, In, Sb) in surface areas of source-drain diffusion regions (6, 7) is set to a value of not smaller than 5×1021/cm3. Alternatively, an alloy film of germanium and silicon containing not less than 20% of germanium, or germanium film, is formed on surface areas of the source-drain diffusion regions (6, 7).

Abstract: Disclosed is a method of manufacturing a semiconductor device capable of improving the reliability of the semiconductor device, which has a field effect transistor having a source-drain structure with a shallow junction. In the process for realizing the reduction of the resistance in a diffusion layer for a source and drain with a shallow junction, in which a part of an amorphous layer formed by the ion implantation for forming a diffusion layer for a source and drain is selectively melted and recrystallized by the use of laser irradiation, in order to prevent the occurrence of defects such as short circuit at a portion where a region to be melted and a gate electrode are overlapped with each other, ion implantation is performed after the formation of a first gate sidewall insulator on a sidewall of the gate electrode so as to obtain a structure in which the amorphous layer is not overlapped with the gate electrode.

Abstract: A high performance super-minituarized double gate SOIMOS being fabricated by re-distributing the impurity with high concentration at the interface of a buried gate insulative film and by aligning the double gate in a self-aligned manner and furthermore, by isolating completely the buried gate electrodes electrically from each other,

Abstract: An impurity having a high electrical activation rate is introduced into a channel region, while an In implanted layer is formed in a very shallow region of the channel region. Impurities B, P are re-distributed such that their maximum impurity concentrations are reached at the same depth of a maximum impurity concentration in the In implanted layer, to form channel impurity regions which electrically act as impurities such as B, P, with a similar depth distribution to that of In. The resulting impurity distribution contributes both to the prevention of a punch-through phenomenon and to a large current driving capability of a highly miniaturized complementary MOS transistor.