Abstract: A stator vane assembly of a gas turbine includes: a stationary member formed to have an annular shape; and a plurality of stator vane segments each including a shroud and a vane body, the plurality of stator vane segments disposed along a circumferential direction of the stationary member at a radially inner side of the stationary member such that a cavity is disposed between the shrouds and the stationary member and the shrouds are disposed adjacent to one another in the circumferential direction of the stationary member. The stationary member has a hole which penetrates through the stationary member from a radially outer side toward the radially inner side, and a center axis of the hole is oriented toward a circumferential-direction end portion of the shroud.

Abstract: The invention provides a solid-state imaging device including a pixel array having a plurality of pixels arranged in a matrix. The pixels can each include a photo diode that generates carriers depending on the intensity of incident light, an accumulation region that accumulates the generated holes, an output transistor that outputs a signal according to threshold voltage that changes depending on the number of carriers accumulated in the accumulation region, and a clear transistor that discharges carriers accumulated in the accumulation region. One of semiconductor regions that form the photo diode and the accumulation region function as a source region of the clear transistor. In the accumulation period, if generated carriers spill from the source region of the clear transistor in the accumulation period, the clear transistor discharges the spilled carriers through a channel of the clear transistor in order to prevent the spilled carriers from entering the accumulation region of adjacent pixels.

Abstract: The invention provides a solid-state imaging device that include a pixel array where a plurality of unit pixels each including a photo diode and an insulated gate field effect transistor for detecting a photocharge are arranged, and a control circuit that controls the operation of the pixel array. The control circuit can apply a predetermined voltage to a source diffused region of the insulated gate field effect transistor and applies voltage by which a channel region becomes a conductive state to a gate electrode to bias a junction region formed of a semiconductor substrate of a first conductivity type and a semiconductor layer of a second conductivity type in a forward direction so as to accumulate a predetermined amount of the charge of a predetermined conductivity type in an accumulation region, and thereby causing the charge of a predetermined conductivity type accumulated in the accumulation region to be discharged.

Abstract: The invention provides a solid-state imaging device that can include a pixel array having a plurality of pixels arranged in a matrix. The pixels can each include a photo diode that generates carriers depending on the intensity of incident light, an accumulation region that accumulates the generated carriers, an insulated-gate output transistor that outputs a signal according to threshold voltage that changes depending on the number of carriers accumulated in the accumulation region, and an insulated-gate clear transistor that discharges carriers accumulated in the accumulation region. The carriers accumulated in the accumulation region are discharged through a channel region of the clear transistor. Accordingly, the invention can provide a technique where carriers in an accumulation region can be easily discharged.

Abstract: The present invention provides a package for enclosing a semiconductor chip and having a plurality of terminals, wherein the terminals are connected with each other by a conductive member in a manner that the electrical connection is disabled by an action of mounting the package on a printed circuit board. During storage, the terminals that are connected by a conductive material are in a short-circuited state until such time immediately before the package is mounted on a printed circuit board. This package prevents high voltage that results from static electricity between the terminals from being applied to circuits of the chip during storage or handling. Therefore, the short-circuited state maintained between the terminals is released after the mounting process, with the result that the operation of the semiconductor chip is not obstructed.

Abstract: The invention provides a solid-state imaging device including a pixel array having a plurality of pixels arranged in a matrix. The pixels can each include a photo diode that generates carriers depending on the intensity of incident light, an accumulation region that accumulates the generated holes, an output transistor that outputs a signal according to threshold voltage that changes depending on the number of carriers accumulated in the accumulation region, and a clear transistor that discharges carriers accumulated in the accumulation region. One of semiconductor regions that form the photo diode and the accumulation region function as a source region of the clear transistor. In the accumulation period, if generated carriers spill from the source region of the clear transistor in the accumulation period, the clear transistor discharges the spilled carriers through a channel of the clear transistor in order to prevent the spilled carriers from entering the accumulation region of adjacent pixels.

Abstract: The invention provides a solid-state imaging device that can include a pixel array having a plurality of pixels arranged in a matrix. The pixels can each include a photo diode that generates carriers depending on the intensity of incident light, an accumulation region that accumulates the generated carriers, an insulated-gate output transistor that outputs a signal according to threshold voltage that changes depending on the number of carriers accumulated in the accumulation region, and an insulated-gate clear transistor that discharges carriers accumulated in the accumulation region. The carriers accumulated in the accumulation region are discharged through a channel region of the clear transistor. Accordingly, the invention can provide a technique where carriers in an accumulation region can be easily discharged.

Abstract: To match where electrons are injected when writing and where holes are injected when erasing in a MONOS-type nonvolatile memory device, two control gates are formed between a word gate on respective intervening ONO gate insulation layers which, in turn, are formed on a substrate. The third layers (silicon oxide layer) are absent over respective portions of the second layers along the lengths of the second gate insulation layers to form shoulders. The electron injection position when writing and the hole injection position when erasing can thus be confined to the neighborhood of the shoulder(s) where the third layer is removed.

Abstract: The invention provides a solid-state imaging device that include a pixel array where a plurality of unit pixels each including a photo diode and an insulated gate field effect transistor for detecting a photocharge are arranged, and a control circuit that controls the operation of the pixel array. The control circuit can apply a predetermined voltage to a source diffused region of the insulated gate field effect transistor and applies voltage by which a channel region becomes a conductive state to a gate electrode to bias a junction region formed of a semiconductor substrate of a first conductivity type and a semiconductor layer of a second conductivity type in a forward direction so as to accumulate a predetermined amount of the charge of a predetermined conductivity type in an accumulation region, and thereby causing the charge of a predetermined conductivity type accumulated in the accumulation region to be discharged.

Abstract: To match where electrons are injected when writing and where holes are injected when erasing in a MONOS-type nonvolatile memory device, two control gates are formed between a word gate on respective intervening ONO gate insulation layers which, in turn, are formed on a substrate. The third layers (silicon oxide layer) are absent over respective portions of the second layers along the lengths of the second gate insulation layers to form shoulders. The electron injection position when writing and the hole injection position when erasing can thus be confined to the neighborhood of the shoulder(s) where the third layer is removed.

Abstract: Certain embodiments relate to a microwave monolithic integrated circuit using a silicon substrate in which parasitic capacitances between inductors and a silicon substrate are sufficiently reduced. A semiconductor device may include a silicon substrate 1, a CMOSFET 200 formed on the silicon substrate 1, and an inductor 100 formed over the silicon substrate 1 through an insulation layer 50. A through hole 300 is formed in the silicon substrate 1 in a portion below the inductor 100.

Abstract: The present invention provides a package for enclosing a semiconductor chip and having a plurality of terminals, wherein the terminals are connected with each other by a conductive member in a manner that the electrical connection is disabled by an action of mounting the package on a printed circuit board. During storage, the terminals that are connected by a conductive material are in a short-circuited state until such time immediately before the package is mounted on a printed circuit board. This package prevents high voltage that results from static electricity between the terminals from being applied to circuits of the chip during storage or handling. Therefore, the short-circuited state maintained between the terminals is released after the mounting process, with the result that the operation of the semiconductor chip is not obstructed.

Abstract: Certain embodiments relate to an inductor that can be manufactured with the existing manufacturing facility, and greatly contributes to a further miniaturization of apparatuses. Embodiments include a semiconductor device having an inductor 100 and a CMOSFET 200 on a SOI. The inductor 100 is obtained by conducting a photolithography and an etching on a cobalt thin film formed on the LOCOS film 6.

Abstract: A microwave ECR plasma etching method and apparatus, including a plasma generating chamber coupled to a separate treatment chamber for supporting a Group II-VI sample to be dry etched, are tailored for the dry etching of Group II-VI compound semiconductors resulting in highly anisotropic etched patterns in Group II-VI materials having vertical side walls taking advantage of the ionicity of the constituents of Group II-VI compounds and utilizing a low ion energy level which will not damage the crystalline integrity of the Group II-VI material. The apparatus may further include counter bias means and/or transverse magnetic field means in a region between the plasma generating chamber and the treatment chamber to improve the reactionary quality of the species and lower the energy level of the species without losing control and directionality of the species flow into the treatment chamber thereby preventing damage to the crystalline structure of the etched II-VI sample.