Patents by Inventor Takashi Takemoto

Takashi Takemoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240311003
    Abstract: According to one embodiment, a memory controller includes a parameter table having entries which respectively correspond to superblock address ranges. The memory controller translates a logical address of data to be written to the memory into a superblock address, calculates compression parameters which correspond to items of data to be written to superblock addresses, writes the compression parameters to the parameter table, and compress data using the parameter table.
    Type: Application
    Filed: March 8, 2024
    Publication date: September 19, 2024
    Applicant: Kioxia Corporation
    Inventors: Kohei OIKAWA, Youhei FUKAZAWA, Keiri NAKANISHI, Sho Kodama, Takashi TAKEMOTO
  • Publication number: 20240303188
    Abstract: A memory system includes a nonvolatile memory and a controller. The controller is configured to maintain an address mapping table including first mapping information indicating correspondence between logical addresses and physical addresses of the nonvolatile memory in units of physical regions each having a predetermined size. The controller, during a write operation compresses write data of the predetermined size into a compressed write data, determines a physical address range in which the compressed write data is to be written, writes the compressed write data into the physical address range and also second mapping information into an area in one or more physical regions spanned by the physical address range, and updates the address mapping table. The second mapping information indicates a logical address of the write data, an information capable of specifying an offset, and a size of the compressed write data.
    Type: Application
    Filed: March 1, 2024
    Publication date: September 12, 2024
    Inventors: Takashi TAKEMOTO, Kensaku YAMAGUCHI, Keiri NAKANISHI, Kohei OIKAWA, Sho KODAMA
  • Patent number: 12057862
    Abstract: According to one embodiment, a data decompression device decodes a code included in compressed data into a symbol. The data decompression device includes a first code length generation unit and a second code length generation unit. The first code length generation unit generates a first code length of a first code included in the compressed data by arithmetic calculation. The second code length generation unit generates a second code length of a second code by using a table. The second code is included in the compressed data. The second code is subsequent to the first code. The table indicates at least the first code and the second code length that is associated with the first code.
    Type: Grant
    Filed: September 7, 2022
    Date of Patent: August 6, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Masato Sumiyoshi, Takashi Takemoto, Keiri Nakanishi
  • Patent number: 11966716
    Abstract: An information processing apparatus includes an annealing control unit, a spin interaction memory, a random number generation unit, and a spin state update unit and obtains a solution by using an Ising model. The annealing control unit controls an annealing step and a parameter of a temperature and a parameter of a self-action. The spin interaction memory stores the interaction coefficient of a spin. The random number generation unit generates a predetermined random number. The spin state update unit includes a spin buffer that stores values of a plurality of spins, an instantaneous magnetic field calculation unit that calculates instantaneous magnetic fields of the plurality of spins, a probability calculation unit that calculates update probabilities of the plurality of spins, and a spin state determination unit that updates the values of the spins based on the update probabilities and a random number.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: April 23, 2024
    Assignees: HITACHI, LTD, NATIONAL UNIVERSITY CORPORATION HOKKAIDO UNIVERSITY
    Inventors: Normann Mertig, Takashi Takemoto, Shinya Takamaeda, Kasho Yamamoto, Masato Motomura, Akira Sakai, Hiroshi Teramoto
  • Publication number: 20240094940
    Abstract: A memory system includes a non-volatile memory and a controller. The controller is configured to perform a write operation of a first data cluster and a first partial overwrite operation of the first data cluster with first overwrite data. The write operation includes compressing and then encrypting the first data cluster, and writing the compressed and encrypted first data cluster into a first physical location of the non-volatile memory. The first partial overwrite operation includes encrypting the first overwrite data without performing compression, reading the compressed and encrypted first data cluster from the first physical location of the non-volatile memory, generating a first composite data cluster with the compressed and encrypted first data cluster read from the first physical location and the encrypted first overwrite data that is not compressed, and writing the first composite data cluster into a second physical location of the non-volatile memory.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 21, 2024
    Inventors: Kensaku YAMAGUCHI, Kiyotaka IWASAKI, Takashi TAKEMOTO, Kohei OIKAWA
  • Patent number: 11922014
    Abstract: According to one embodiment, a controller of a memory system manages a first table maintaining a relationship between a logical address and a physical address, compresses first data corresponding to a first address of a write command, specifies a size of second data obtained by compressing the first data, determines allocation of the second data on a memory based on the size of the second data, stores a second address corresponding to a physical area where a head of the second data is stored and a physical area number used to store the second data in an entry of the first logical address in the first table, and stores the first address, offset of a position of a leader of the second data in the physical area, and the size of the second data in the physical area.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: March 5, 2024
    Assignee: Kioxia Corporation
    Inventors: Keiri Nakanishi, Kensaku Yamaguchi, Takashi Takemoto
  • Patent number: 11875901
    Abstract: A registration apparatus is configured to access a network formed of a set of first nodes and first edges, the first nodes each representing a first feature vector including a plurality of elements, the first edges each coupling two first nodes representing two first feature vectors to each other based on two first feature vectors, a processor in the registration apparatus is configured to execute: obtaining processing of obtaining a second feature vector; and registration processing of registering a second node representing the second feature vector to the network based on a similarity relationship among third feature vectors in a set of third feature vectors included in the set of first feature vectors, and coupling the second node and a third node representing the third feature vector to each other with a second edge, the number of third feature vectors being smaller than the number of first feature vectors.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: January 16, 2024
    Assignee: HITACHI, LTD.
    Inventors: Miaomei Lei, Takahiro Nakamura, Daisuke Suzuki, Takashi Takemoto
  • Publication number: 20230412190
    Abstract: An entropy code encoder includes a register and first, second, third, and fourth arithmetic circuits. The first arithmetic circuit is configured to output, based on an input symbol, a first value corresponding to an appearance frequency of the input symbol and a second value corresponding to a cumulative distribution of the first value. The second arithmetic circuit is configured to output a third value corresponding to division of a value of bits in the register by the first value. The third arithmetic circuit is configured to output a fourth value obtained by adding the second value to a bit-shifted value of the third value, to update a value in the register. The fourth arithmetic circuit is configured to compare the value of upper bits in the register and the first value and output a value of lower bits in the register as a compressed data stream.
    Type: Application
    Filed: March 3, 2023
    Publication date: December 21, 2023
    Inventor: Takashi TAKEMOTO
  • Publication number: 20230305718
    Abstract: A memory system includes a nonvolatile memory and a controller. The controller is configured to segment data into clusters, perform a compression with respect to each of the clusters, allocate the clusters subjected to the compression to encoding frames in accordance with a predetermined rule. According to the predetermined rule, at least a part of a cluster is allocated to a vacant space of an encoding frame in a first state, when a predetermined condition is met, and an entirety of a cluster is allocated to an encoding frame in a second state, when no encoding frame in the first state exists or when the predetermined condition is not met. The controller is further configured to encode data in each of the encoding frames and write the encoded data into the nonvolatile memory.
    Type: Application
    Filed: August 30, 2022
    Publication date: September 28, 2023
    Inventors: Takashi TAKEMOTO, Kensaku YAMAGUCHI
  • Publication number: 20230291418
    Abstract: According to one embodiment, a data decompression device decodes a code included in compressed data into a symbol. The data decompression device includes a first code length generation unit and a second code length generation unit. The first code length generation unit generates a first code length of a first code included in the compressed data by arithmetic calculation. The second code length generation unit generates a second code length of a second code by using a table. The second code is included in the compressed data. The second code is subsequent to the first code. The table indicates at least the first code and the second code length that is associated with the first code.
    Type: Application
    Filed: September 7, 2022
    Publication date: September 14, 2023
    Inventors: Masato SUMIYOSHI, Takashi TAKEMOTO, Keiri NAKANISHI
  • Publication number: 20230282359
    Abstract: Health data is made available to a private business operator to improve health of a resident. A data processing system includes a storage device accessible by an arithmetic processing device; a reception unit configured to receive input data; an information conversion unit configured to convert the input data; a health prediction model generated based on nutrient information and an outcome; and an output unit configured to output information of a subject based on a prediction result generated by the health prediction model. The reception unit receives the input data relating to a customer of a business operator, the information conversion unit converts the input data into customer nutrient information indicating a nutrient ingested by the customer, the health prediction model predicts health based on the customer nutrient information, and the output unit outputs advice for the health of the subject to the business operator based on the prediction result.
    Type: Application
    Filed: January 23, 2023
    Publication date: September 7, 2023
    Inventors: Takahiro NAKAMURA, Takashi TAKEMOTO, Miaomei LEI, Keisuke TERADA
  • Publication number: 20230282335
    Abstract: An object of the invention is to improve reliability of an annotation. A collation apparatus includes: a grouping processing unit configured to group, based on each explanatory variable of a sample group, the sample group into a first group indicating a first classification and a second group indicating a second classification having a lower evaluation than the first classification; a collation unit configured to collate the classification of the first group and the second group that are obtained by the grouping processing unit with a classification identified by each objective variable of the sample group; and an output unit configured to output a collation result obtained by the collation unit.
    Type: Application
    Filed: January 25, 2023
    Publication date: September 7, 2023
    Inventors: Miaomei LEI, Takahiro NAKAMURA, Takashi TAKEMOTO, Michinori MAYAMA
  • Publication number: 20230142776
    Abstract: An analysis device in a parent-child health management system receives a sensor output from a sensor terminal and an answer to a questionnaire from a user terminal. At least one of parent's life information and child's life information is analyzed based on the answer to the questionnaire to generate a life information analysis result. A sensor output analysis unit generates, based on the sensor output, a sensing result including at least one of a parent-child relationship, a parent's health condition, and a child's health condition. A health estimation unit is configured to compare the life information analysis result and the sensing result with a predetermined criterion to estimate at least one of a parent-child state, a parent's state, and a child's state. An output unit is configured to select a questionnaire and advice corresponding to the estimated state and output the selected questionnaire and advice to the user terminal.
    Type: Application
    Filed: March 12, 2021
    Publication date: May 11, 2023
    Inventors: Takahiro NAKAMURA, Takashi TAKEMOTO, Masanori YOSHINO, Tokiyoshi AYABE, Takashi KIMURA, Hirohisa IZUMI, Fuka TABATA
  • Publication number: 20230142767
    Abstract: According to one embodiment, a controller of a memory system manages a first table maintaining a relationship between a logical address and a physical address, compresses first data corresponding to a first address of a write command, specifies a size of second data obtained by compressing the first data, determines allocation of the second data on a memory based on the size of the second data, stores a second address corresponding to a physical area where a head of the second data is stored and a physical area number used to store the second data in an entry of the first logical address in the first table, and stores the first address, offset of a position of a leader of the second data in the physical area, and the size of the second data in the physical area.
    Type: Application
    Filed: September 6, 2022
    Publication date: May 11, 2023
    Inventors: Keiri NAKANISHI, Kensaku YAMAGUCHI, Takashi TAKEMOTO
  • Publication number: 20230118421
    Abstract: A mother and child health management system is connected to a plurality of terminals and includes: a reception unit configured to receive, as analysis information, information from each of the plurality of terminals and biological information from a medical care institution; a classification unit configured to identify, based on an analysis result of the analysis information, state values indicating a state of a mother, a state of a child, and a state between the mother and the child; an access authority management section configured to identify, based on each of the state values, a community to which a family including a user of the each of the plurality of terminals belongs, and configured to provide the terminal with an access authority to receive a display of a solution related to the community; and a display unit configured to display the solution related to the community on the terminal.
    Type: Application
    Filed: March 12, 2021
    Publication date: April 20, 2023
    Inventors: Takahiro NAKAMURA, Takashi TAKEMOTO, Masanori YOSHINO, Tokiyoshi AYABE, Takashi KIMURA, Hirohisa IZUMI, Fuka TABATA
  • Patent number: 11476504
    Abstract: Provided is an all-solid-state battery which is configured to suppress an increase in the resistance of the all-solid-state battery and which is configured to suppress the peeling-off of the solid electrolyte layer. Disclosed is an all-solid-state battery comprising: a cathode comprising a cathode layer, an anode comprising an anode layer, and a solid electrolyte layer disposed between the cathode layer and the anode layer, wherein a width of the cathode layer is smaller than a width of the anode layer and a width of the solid electrolyte layer; wherein the solid electrolyte layer comprises a non-facing portion where the solid electrolyte layer does not face the cathode layer and a facing portion where the solid electrolyte layer faces the cathode layer; and wherein a binder content of the non-facing portion is larger than a binder content of the facing portion.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: October 18, 2022
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Motoshi Isono, Takashi Takemoto, Kazuo Yaso
  • Publication number: 20220262467
    Abstract: A health data processing system in which an arithmetic unit can gain access to a database storing basic data of residents, health data of residents, and social capital index measurement data is provided. The health data processing system includes: an individual health condition analysis part which analyzes an individual health condition being each resident's health condition with use of the health data; a regional health condition analysis part which analyzes a regional health condition being a health condition of residents who belong to a region with use of the health data; an SCI derivation part which derives a regional SCI being a social capital index for every region with use of the social capital index measurement data; and an individually providing information generation part which generates information contributing to residents' health with use of the individual health condition, the regional health condition, and the regional SCI.
    Type: Application
    Filed: January 14, 2022
    Publication date: August 18, 2022
    Inventors: Takahiro NAKAMURA, Jyunichiro WATANABE, Takashi TAKEMOTO, Akiko TAMAKOSHI, Takashi KIMURA
  • Publication number: 20220093265
    Abstract: A registration apparatus is configured to access a network formed of a set of first nodes and first edges, the first nodes each representing a first feature vector including a plurality of elements, the first edges each coupling two first nodes representing two first feature vectors to each other based on two first feature vectors, a processor in the registration apparatus is configured to execute: obtaining processing of obtaining a second feature vector; and registration processing of registering a second node representing the second feature vector to the network based on a similarity relationship among third feature vectors in a set of third feature vectors included in the set of first feature vectors, and coupling the second node and a third node representing the third feature vector to each other with a second edge, the number of third feature vectors being smaller than the number of first feature vectors.
    Type: Application
    Filed: March 11, 2021
    Publication date: March 24, 2022
    Applicant: Hitachi, Ltd.
    Inventors: Miaomei LEI, Takahiro NAKAMURA, Daisuke SUZUKI, Takashi TAKEMOTO
  • Publication number: 20220091820
    Abstract: A structure of floating-point number data stored in a storage medium according to an embodiment is provided with a first partial code obtained by encoding all or part of an exponent of a floating-point number using variable-length coding, and a second partial code including a significand of the floating-point number. The length of the combined code of the first partial code and the second partial code is fixed, and the end bit of the first partial code and the least significant hit of the second partial code are adjacent to each other.
    Type: Application
    Filed: August 20, 2021
    Publication date: March 24, 2022
    Inventor: Takashi Takemoto
  • Patent number: 11100904
    Abstract: According to embodiments, an image drawing apparatus includes: an SRAM; and a transaction conversion unit configured to convert a transaction based on a virtual address indicating a pixel position in a storage area of the SRAM into a transaction based on a physical address in the SRAM. When the storage area is divided into a plurality of windows in a row direction and a column direction so that each window includes one or more lines, and an assigned area which is assigned the physical address in the SRAM is set in each of the windows, the transaction conversion unit converts the transaction based on the virtual address into the transaction based on the physical address based on whether the pixel position indicated by the virtual address is in the assigned area.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: August 24, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Takashi Takemoto, Yuji Hisamatsu, Shinichi Shionoya, Michio Katsuhara