Abstract: There is an SRAM which can perform a high-speed read operation at a low power supply voltage and which can simplify a circuit configuration and manufacturing steps. When signals at levels “H” and “L” are output from a flip-flop to storage nodes, respectively, the threshold voltages of first and second N-channel MOS transistors having channel regions connected to the storage node decrease to improve the current drive capabilities of the transistors. The second N-channel MOS transistor is set in an ON state by the level of the storage node. In this case, when a word line goes to level “H”, the first N-channel MOS transistor is turned on, and a bit line is drawn in a ground potential at a high speed.

Abstract: A semiconductor memory which operates at low power supply voltage with lower power consumption without decreasing writes rate is provided. During data read, a virtual ground line VGj provided to correspond to a bit line pair BLj, /BLj of a read target memory cell 11ij is connected to a ground voltage GND through a transistor 31j. As a result, the bit line BLj (or /BLj) corresponding to “L” level is connected to the ground voltage GND through an acceleration circuit AC provided in the memory cell 11ij to thereby accelerate read rate. During data write, the virtual ground line VGj corresponding to the write target bit line pair BLj, /BLj is connected to a power supply voltage VDD through a transistor 33j. As a result, a current is prevented from flowing from the bit line BLj (or /BLj) at “H” level to the virtual ground line VGj and the write rate is not decreased.

Abstract: A semiconductor memory device capable of saving power supply voltage and power consumption without increasing the forming area of memory cell array by using MTCMOS technology. In writing data in a memory cell 50-21, a signal RE is turned “H” level, an NMOS 61-1 is turned off and a virtual ground line VGND1 is turned into floating state. When the signal RE is “H” level, the output level of an AND circuit 64-2 turns “L” level and NMOS 55a and 55b turn off. NMOS 53 and 54 turn on by “H” level of a word line WL2 and data in a bit line pair BL1 and BL/ is held on nodes N11 and N12. In reading out data, the signal RE is turned “L” level. When the NMOS 61-1 turns on and the VGND 1 becomes connected to GND, an acceleration circuit 55 accelerates the speed of readout operation.

Abstract: Using an endoscope system, a surgeon A holds an endoscope with a TV camera (hereinafter, an endoscope) and a therapeutic appliance such as forceps and carries out a surgical procedure while viewing a first monitor. A surgeon B holds a therapeutic appliance such as forceps and carries out the surgical procedure while viewing a second monitor. A video signal sent from the TV camera of the endoscope is fed to and processed by an image processing apparatus, and displayed on each of the first and second monitors. The image processing apparatus transfers the video signal sent from the endoscope to each of an image inverting circuit and a selector switch. The image inverting circuit inverts an image (laterally (to produce a mirror image), vertically, or vertically and laterally (180°)), and supplies a processed video signal to the selector switch.

Abstract: A semiconductor memory which operates at low power supply voltage with lower power consumption without decreasing writes rate is provided. During data read, a virtual ground line VGj provided to correspond to a bit line pair BLj, /BLj of a read target memory cell 11ij is connected to a ground voltage GND through a transistor 31j. As a result, the bit line BLj (or /BLj) corresponding to “L” level is connected to the ground voltage GND through an acceleration circuit AC provided in the memory cell 11ij to thereby accelerate read rate. During data write, the virtual ground line VGj corresponding to the write target bit line pair BLj, /BLj is connected to a power supply voltage VDD through a transistor 33j. As a result, a current is prevented from flowing from the bit line BLj (or /BLj) at “H” level to the virtual ground line VGj and the write rate is not decreased.

Abstract: A battery power source device including a plurality of rechargeable batteries (1) having a laminated sheet as an outer case, and having extended positive and negative electrode leads of a metal foil is provided. A circuit board (3) and a plurality of rechargeable batteries are positioned in a pack case (2), a soldering land (21) is formed in the extending direction of the positive and negative electrode leads (11) and (12) of the rechargeable batteries, and a circuit pattern formed on the circuit board allows the circuit board and the rechargeable batteries to be connected without applying force in the bending or distortional direction to the positive and negative electrode leads of a foil.

Abstract: This invention provides a semiconductor memory device capable of saving power supply voltage and power consumption without increasing the forming area of memory cell array by using MTCMOS technology. In writing data in a memory cell 50-21, a signal RE is turned “H” level, an NMOS 61-1 is turned off and a virtual ground line VGND1 is turned into floating state. When the signal RE is “H” level, the output level of an AND circuit 64-2 turns “L” level and NMOS 55a and 55b turn off. NMOS 53 and 54 turn on by “H” level of a word line WL2 and data in a bit line pair BL1 and BL/ is held on nodes N11 and N12. In reading out data, the signal RE is turned “L” level. When the NMOS 61-1 turns on and the VGND 1 becomes connected to GND, an acceleration circuit 55 accelerates the speed of readout operation.

Abstract: A battery pack that reduces thickness and lightens weight as required for battery power sources of portable electronic equipment. A battery pack is constituted by accommodating a battery and battery protection device between a top case and bottom case forming a pack case. Since the battery is formed accommodated within an external casing wherein positive and negative electrode plates are formed by laminated sheet, reduced thickness and reduced weight of battery pack can be achieved. Also, since the face of bottom case opposite the battery is formed as a resiliently deformable face which is formed of small thickness, when expansion takes place such that the thickness of the battery as a whole increases, resiliently deformable face deforms maintaining a planar condition by resilient deformation, so that there is no possibility of an adverse effect on the equipment due to drum-shaped swelling being produced in battery pack, by such swelling.