Patents by Inventor Takashi Tange

Takashi Tange has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220006265
    Abstract: A nitride semiconductor laser device of one embodiment of the present disclosure includes a single-crystal substrate, a base layer, a sheet-shaped structure, a light emitting layer, and a resonator mirror. The single-crystal substrate extends in one direction. The base layer is provided on the single-crystal substrate and includes a nitride semiconductor. The sheet-shaped structure is provided on the base layer to stand in a direction perpendicular to the base layer. The sheet-shaped structure has an area of a side surface that is greater than an area of an upper surface. The side surface extends in a longitudinal direction of the single-crystal substrate. The sheet-shaped structure includes a nitride semiconductor. The light emitting layer is provided at least on the side surface of the sheet-shaped structure. The light emitting layer includes a nitride semiconductor. The resonator mirror is provided by a pair of end surfaces of the sheet-shaped structure that oppose each other in the longitudinal direction.
    Type: Application
    Filed: October 25, 2019
    Publication date: January 6, 2022
    Inventors: TAKASHI TANGE, KUNIHIKO TASAI, KOTA TOKUDA
  • Patent number: 10546975
    Abstract: A semiconductor optical device has a multilayer structure 30 including a first compound semiconductor layer 31, an active layer 33, and a second compound semiconductor layer 32. A second electrode 42 is formed on the second compound semiconductor layer 32 through a contact layer 34. The contact layer 34 has a thickness of four or less atomic layers. When an interface between the contact layer 34 and the second compound semiconductor layer 32 is an xy-plane, a lattice constant along an x-axis of crystals constituting an interface layer 32A which is a part of the second compound semiconductor layer in contact with the contact layer 34 is x2, a lattice constant along a z-axis is z2, a length along an x-axis in one unit of crystals constituting the contact layer 34 is xc?, and a length along the z-axis is zc?, (zc?/xc?)>(z2/x2) is satisfied.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: January 28, 2020
    Assignee: Sony Corporation
    Inventors: Takashi Tange, Tatsushi Hamaguchi, Masaru Kuramoto
  • Publication number: 20190148594
    Abstract: A semiconductor optical device has a multilayer structure 30 including a first compound semiconductor layer 31, an active layer 33, and a second compound semiconductor layer 32. A second electrode 42 is formed on the second compound semiconductor layer 32 through a contact layer 34. The contact layer 34 has a thickness of four or less atomic layers. When an interface between the contact layer 34 and the second compound semiconductor layer 32 is an xy-plane, a lattice constant along an x-axis of crystals constituting an interface layer 32A which is a part of the second compound semiconductor layer in contact with the contact layer 34 is x2, a lattice constant along a z-axis is z2, a length along an x-axis in one unit of crystals constituting the contact layer 34 is xc?, and a length along the z-axis is zc?, (zc?/xc?)>(z2/x2) is satisfied.
    Type: Application
    Filed: December 20, 2018
    Publication date: May 16, 2019
    Inventors: Takashi TANGE, Tatsushi HAMAGUCHI, Masaru KURAMOTO
  • Patent number: 10170667
    Abstract: A semiconductor optical device has a multilayer structure 30 including a first compound semiconductor layer 31, an active layer 33, and a second compound semiconductor layer 32. A second electrode 42 is formed on the second compound semiconductor layer 32 through a contact layer 34. The contact layer 34 has a thickness of four or less atomic layers. When an interface between the contact layer 34 and the second compound semiconductor layer 32 is an xy-plane, a lattice constant along an x-axis of crystals constituting an interface layer 32A which is a part of the second compound semiconductor layer in contact with the contact layer 34 is x2, a lattice constant along a z-axis is z2, a length along an x-axis in one unit of crystals constituting the contact layer 34 is xc?, and a length along the z-axis is zc?, (zc?/xc?)>(z2/x2) is satisfied.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: January 1, 2019
    Assignee: Sony Corporation
    Inventors: Takashi Tange, Tatsushi Hamaguchi, Masaru Kuramoto
  • Publication number: 20180190866
    Abstract: A semiconductor optical device has a multilayer structure 30 including a first compound semiconductor layer 31, an active layer 33, and a second compound semiconductor layer 32. A second electrode 42 is formed on the second compound semiconductor layer 32 through a contact layer 34. The contact layer 34 has a thickness of four or less atomic layers. When an interface between the contact layer 34 and the second compound semiconductor layer 32 is an xy-plane, a lattice constant along an x-axis of crystals constituting an interface layer 32A which is a part of the second compound semiconductor layer in contact with the contact layer 34 is x2, a lattice constant along a z-axis is z2, a length along an x-axis in one unit of crystals constituting the contact layer 34 is xc?, and a length along the z-axis is zc?, (zc?/xc?)>(z2/x2) is satisfied.
    Type: Application
    Filed: February 12, 2018
    Publication date: July 5, 2018
    Inventors: Takashi TANGE, Tatsushi HAMAGUCHI, Masaru KURAMOTO
  • Patent number: 9917228
    Abstract: A semiconductor optical device has a multilayer structure 30 including a first compound semiconductor layer 31, an active layer 33, and a second compound semiconductor layer 32. A second electrode 42 is formed on the second compound semiconductor layer 32 through a contact layer 34. The contact layer 34 has a thickness of four or less atomic layers. When an interface between the contact layer 34 and the second compound semiconductor layer 32 is an xy-plane, a lattice constant along an x-axis of crystals constituting an interface layer 32A which is a part of the second compound semiconductor layer in contact with the contact layer 34 is x2, a lattice constant along a z-axis is z2, a length along an x-axis in one unit of crystals constituting the contact layer 34 is xc?, and a length along the z-axis is zc?, (zc?/xc?)>(z2/x2) is satisfied.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: March 13, 2018
    Assignee: Sony Corporation
    Inventors: Takashi Tange, Tatsushi Hamaguchi, Masaru Kuramoto
  • Patent number: 9905719
    Abstract: A multi-junction solar cell that is lattice-matched with a base, and that includes a sub-cell having a desirable band gap is provided. A plurality of sub-cells are laminated, each including first and second compound semiconductor layers. At least one predetermined sub-cell is configured of first layers and a second layer. In each of the first layers, a 1-A layer and a 1-B layer are laminated. In the second layer, a 2-A layer and a 2-B layer are laminated. A composition A of the 1-A layer and the 2-A layer is determined based on a value of a band gap of the predetermined sub-cell. A composition B of the 1-B layer and the 2-B layer is determined based on a difference between a base lattice constant of the base and a lattice constant of the composition A. Thicknesses of 1-B layer and 2-B layer are determined based on difference between base lattice constant and a lattice constant of composition B, and on thickness of the 1-A layer and thickness of 2-A layer.
    Type: Grant
    Filed: September 3, 2012
    Date of Patent: February 27, 2018
    Assignee: Sony Corporation
    Inventors: Hiroshi Yoshida, Masao Ikeda, Shiro Uchida, Takashi Tange, Masaru Kuramoto, Masayuki Arimochi, Hui Yang, Shulong Lu, Xinhe Zheng
  • Publication number: 20170141267
    Abstract: A semiconductor optical device has a multilayer structure 30 including a first compound semiconductor layer 31, an active layer 33, and a second compound semiconductor layer 32. A second electrode 42 is formed on the second compound semiconductor layer 32 through a contact layer 34. The contact layer 34 has a thickness of four or less atomic layers. When an interface between the contact layer 34 and the second compound semiconductor layer 32 is an xy-plane, a lattice constant along an x-axis of crystals constituting an interface layer 32A which is a part of the second compound semiconductor layer in contact with the contact layer 34 is x2, a lattice constant along a z-axis is z2, a length along an x-axis in one unit of crystals constituting the contact layer 34 is xc?, and a length along the z-axis is zc?, (zc?/xc?)>(z2/x2) is satisfied.
    Type: Application
    Filed: April 17, 2015
    Publication date: May 18, 2017
    Applicant: Sony Corporation
    Inventors: Takashi TANGE, Tatsushi HAMAGUCHI, Masaru KURAMOTO
  • Publication number: 20140345681
    Abstract: There is provided a multi-junction solar cell that reduces contact resistance of a junction portion and is capable of performing energy conversion with high efficiency. The multi-junction solar cell includes a plurality of sub-cells 11, 12, 13, and 14 that are laminated, the plurality of sub-cells 11, 12, 13, and 14 being configured of a plurality of compound semiconductor layers 11A, 11B, 11C, 12A, 12B, 12C, 13A, 13B, 13C, 14A, 14B, and 14C that are laminated. Amorphous connection layers 20A and 20B made of electrically-conductive material are provided in at least one place between the sub-cells 12 and 13 adjacent to each other.
    Type: Application
    Filed: September 3, 2012
    Publication date: November 27, 2014
    Inventors: Hiroshi Yoshida, Masao Ikeda, Shiro Uchida, Takashi Tange, Masaru Kuramoto, Masayuki Arimochi, Hui Yang, Shulong Lu, Xinhe Zheng
  • Publication number: 20140345680
    Abstract: A multi-junction solar cell that is lattice-matched with a base, and that includes a sub-cell having a desirable band gap is provided. A plurality of sub-cells are laminated, each including first and second compound semiconductor layers. At least one predetermined sub-cell is configured of first layers and a second layer. In each of the first layers, a 1-A layer and a 1-B layer are laminated. In the second layer, a 2-A layer and a 2-B layer are laminated. A composition A of the 1-A layer and the 2-A layer is determined based on a value of a band gap of the predetermined sub-cell. A composition B of the 1-B layer and the 2-B layer is determined based on a difference between a base lattice constant of the base and a lattice constant of the composition A. Thicknesses of 1-B layer and 2-B layer are determined based on difference between base lattice constant and a lattice constant of composition B, and on thickness of the 1-A layer and thickness of 2-A layer.
    Type: Application
    Filed: September 3, 2012
    Publication date: November 27, 2014
    Inventors: Hiroshi Yoshida, Masao Ikeda, Shiro Uchida, Takashi Tange, Masaru Kuramoto, Masayuki Arimochi, Hui Yang, Shulong Lu, Xinhe Zheng
  • Publication number: 20130022070
    Abstract: The present invention relates to a semiconductor laser device capable of reliably suppressing degradation of an end face due to interface oxidation and distortion application, and to a manufacturing method of the same. The semiconductor laser device has a laser structure portion 107 having opposite resonator faces 108 and 109, and protecting films 110 and 120 formed on at least one of the opposite resonator end faces, wherein the protecting films 110 and 120 are formed of nitride dielectric films having a multistage structure including amorphous layers 111 and 121 and polycrystal layers 112 and 122 in crystal structure, respectively, from aside in contact with the resonator faces.
    Type: Application
    Filed: November 11, 2011
    Publication date: January 24, 2013
    Applicant: SONY CORPORATION
    Inventors: Takashi Tange, Shigetaka Tomiya
  • Publication number: 20100308349
    Abstract: A light-emitting diode with (a) a substrate having at least one recessed portion on one main surface; (b) a sixth nitride-based III-V group compound semiconductor layer grown on the substrate without forming a space in the recessed portion; and (c) a third nitride-based III-V group compound semiconductor layer of a first conduction type, an active layer and a fourth nitride-based III-V group compound semiconductor layer of a second conduction type formed over the sixth nitride-based III-V group compound semiconductor layer, wherein, a dislocation occurring, in the sixth nitride-based III-V group compound semiconductor layer, from an interface with a bottom surface of the recessed portion in a direction vertical to the one main surface arrives at an inclined face or its vicinity of a triangle having the bottom surface of the recessed portion as a base and bends in a direction parallel to the one main surface.
    Type: Application
    Filed: June 9, 2010
    Publication date: December 9, 2010
    Applicant: Sony Corporation
    Inventors: Akira Ohmae, Shigetaka Tomiya, Yuki Maeda, Michinori Shiomi, Takaaki Ami, Takao Miyajima, Katsunori Yanashima, Takashi Tange, Atsushi Yasuda
  • Patent number: 7754504
    Abstract: A method for making a light-emitting diode, which including the steps of: providing a substrate having at least one recessed portion on one main surface and growing a first nitride-based III-V group compound semiconductor layer through a state of making a triangle in section having a bottom surface of the recessed portion as a base thereby burying the recessed portion; laterally growing a second nitride-based III-V group compound semiconductor layer from the first nitride-based III-V group compound semiconductor layer over the substrate; and successively growing a third nitride-based III-V group compound semiconductor layer of a first conduction type, an active layer and a fourth nitride-based III-V group compound semiconductor layer of a second conduction type on the second nitride-based III-V group compound semiconductor layer.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: July 13, 2010
    Assignee: Sony Corporation
    Inventors: Akira Ohmae, Shigetaka Tomiya, Yuki Maeda, Michinori Shiomi, Takaaki Ami, Takao Miyajima, Katsunori Yanashima, Takashi Tange, Atsushi Yasuda
  • Publication number: 20060258027
    Abstract: A method for making a light-emitting diode, which including the steps of: providing a substrate having at least one recessed portion on one main surface and growing a first nitride-based III-V group compound semiconductor layer through a state of making a triangle in section having a bottom surface of the recessed portion as a base thereby burying the recessed portion; laterally growing a second nitride-based III-V group compound semiconductor layer from the first nitride-based III-V group compound semiconductor layer over the substrate; and successively growing a third nitride-based III-V group compound semiconductor layer of a first conduction type, an active layer and a fourth nitride-based III-V group compound semiconductor layer of a second conduction type on the second nitride-based III-V group compound semiconductor layer.
    Type: Application
    Filed: May 16, 2006
    Publication date: November 16, 2006
    Inventors: Akira Ohmae, Shigetaka Tomiya, Yuki Maeda, Michinori Shiomi, Takaaki Ami, Takao Miyajima, Katsunori Yanashima, Takashi Tange, Atsushi Yasuda