Abstract: A semiconductor integrated circuit includes a substrate including a first wiring layer and a second wiring layer that is separated from the first wiring layer in a stacking direction, and an equalization circuit formed on the substrate to amplify a signal level of a part of a frequency bandwidth included in a differential input signal including a first signal and a second signal, and output a differential output signal including a third signal and a fourth signal, in which the equalization circuit includes a first transistor, a first inductor element, a second transistor, and a second inductor element, each of the first inductor element and the second inductor element has a first inductor portion, a second inductor portion, and a third inductor portion, the first inductor portion and the second inductor portion include single-layer winding coils, a third end portion of the third inductor portion is electrically connected to a first end portion of the first inductor portion, and a fourth end portion of the thi

Abstract: A semiconductor integrated circuit includes a substrate including a first wiring layer and a second wiring layer that is separated from the first wiring layer in a stacking direction, and an equalization circuit formed on the substrate to amplify a signal level of a part of a frequency bandwidth included in a differential input signal including a first signal and a second signal, and output a differential output signal including a third signal and a fourth signal, in which the equalization circuit includes a first transistor, a first inductor element, a second transistor, and a second inductor element, each of the first inductor element and the second inductor element has a first inductor portion, a second inductor portion, and a third inductor portion, the first inductor portion and the second inductor portion include single-layer winding coils, a third end portion of the third inductor portion is electrically connected to a first end portion of the first inductor portion, and a fourth end portion of the thi

Abstract: A memory system includes first, second, third, and fourth nonvolatile memory, a memory controller configured to modulate write data for the first and second memory into a first time slot of a data signal according to an allocation scheme, and modulate write data for the third and fourth memory into a second time slot of the data signal according to the allocation scheme, a first bridge circuit configured according to the allocation scheme to extract first write data from the first time slot, a second bridge circuit configured according to the allocation scheme to extract second write data from the first time slot, a third bridge circuit configured according to the allocation scheme to extract third write data from the second time slot, and a fourth bridge circuit configured according to the allocation scheme to extract fourth write data from the second time slot.

Abstract: A semiconductor integrated circuit includes a first circuit configured to carry out digital-to-analog conversion on input data; a high-pass filter configured to reduce a component, the component having a frequency lower than a predetermined cutoff frequency, in delayed input data obtained by delaying the input data, and output the delayed input data; a second circuit configured to carryout the digital-to-analog conversion on the delayed input data that passes through the high-pass filter; and a third circuit configured to drive a transmission signal, the transmission signal based on an addition signal obtained by adding an output signal of the first circuit and an output signal of the second circuit.

Abstract: A semiconductor integrated circuit includes a first circuit configured to carry out digital-to-analog conversion on input data; a high-pass filter configured to reduce a component, the component having a frequency lower than a predetermined cutoff frequency, in delayed input data obtained by delaying the input data, and output the delayed input data; a second circuit configured to carryout the digital-to-analog conversion on the delayed input data that passes through the high-pass filter; and a third circuit configured to drive a transmission signal, the transmission signal based on an addition signal obtained by adding an output signal of the first circuit and an output signal of the second circuit.

Abstract: A memory system includes first, second, third, and fourth nonvolatile memory, a memory controller configured to modulate write data for the first and second memory into a first time slot of a data signal according to an allocation scheme, and modulate write data for the third and fourth memory into a second time slot of the data signal according to the allocation scheme, a first bridge circuit configured according to the allocation scheme to extract first write data from the first time slot, a second bridge circuit configured according to the allocation scheme to extract second write data from the first time slot, a third bridge circuit configured according to the allocation scheme to extract third write data from the second time slot, and a fourth bridge circuit configured according to the allocation scheme to extract fourth write data from the second time slot.

Abstract: A receiving device includes first, second, and third circuits, and a processing circuit. The first circuit is configured to calculate a phase difference between a first clock signal and a data signal, which is a signal modulated by pulse-amplitude modulation. The second circuit is configured to generate a second clock signal based on the first clock signal and the phase difference. Jitter is added to second clock signal. The third circuit is configured to demodulate the data signal by comparing an amplitude of each pulse of the data signal with a threshold value at a timing synchronized to the second clock signal added the jitter. The processing circuit is configured to count the number of errors in the demodulated data signal and then calibrate the threshold value based on the counted number of errors.

Abstract: A memory system includes first, second, third, and fourth nonvolatile memory, a memory controller configured to modulate write data for the first and second memory into a first time slot of a data signal according to an allocation scheme, and modulate write data for the third and fourth memory into a second time slot of the data signal according to the allocation scheme, a first bridge circuit configured according to the allocation scheme to extract first write data from the first time slot, a second bridge circuit configured according to the allocation scheme to extract second write data from the first time slot, a third bridge circuit configured according to the allocation scheme to extract third write data from the second time slot, and a fourth bridge circuit configured according to the allocation scheme to extract fourth write data from the second time slot.

Abstract: A receiving device includes first, second, and third circuits, and a processing circuit. The first circuit is configured to calculate a phase difference between a first clock signal and a data signal, which is a signal modulated by pulse-amplitude modulation. The second circuit is configured to generate a second clock signal based on the first clock signal and the phase difference. Jitter is added to second clock signal. The third circuit is configured to demodulate the data signal by comparing an amplitude of each pulse of the data signal with a threshold value at a timing synchronized to the second clock signal added the jitter. The processing circuit is configured to count the number of errors in the demodulated data signal and then calibrate the threshold value based on the counted number of errors.

Abstract: According to one embodiment, a transmitter includes a 1st circuit configured to execute a 1st band limitation by waveform shaping in a time region with respect to 1st data relating to a 1st channel to generate a 1st signal; a 2nd circuit configured to execute a 2nd band limitation by the waveform shaping in the time region with respect to 2nd data relating to a 2nd channel to generate a 2nd signal; a 3rd circuit configured to generate a 3rd signal based on the 1st signal and a 1st frequency relating to the 1st channel; a 4th circuit configured to generate a 4th signal based on the 2nd signal and a 2nd frequency relating to the 2nd channel; and a 5th circuit configured to generate a 5th signal by multiplexing the 3rd signal and the 4th signal.

Abstract: A memory system includes first, second, third, and fourth nonvolatile memory, a memory controller configured to modulate write data for the first and second memory into a first time slot of a data signal according to an allocation scheme, and modulate write data for the third and fourth memory into a second time slot of the data signal according to the allocation scheme, a first bridge circuit configured according to the allocation scheme to extract first write data from the first time slot, a second bridge circuit configured according to the allocation scheme to extract second write data from the first time slot, a third bridge circuit configured according to the allocation scheme to extract third write data from the second time slot, and a fourth bridge circuit configured according to the allocation scheme to extract fourth write data from the second time slot.

Abstract: According to one embodiment, a transmitter includes a 1st circuit configured to execute a 1st band limitation by waveform shaping in a time region with respect to 1st data relating to a 1st channel to generate a 1st signal; a 2nd circuit configured to execute a 2nd band limitation by the waveform shaping in the time region with respect to 2nd data relating to a 2nd channel to generate a 2nd signal; a 3rd circuit configured to generate a 3rd signal based on the 1st signal and a 1st frequency relating to the 1st channel; a 4th circuit configured to generate a 4th signal based on the 2nd signal and a 2nd frequency relating to the 2nd channel; and a 5th circuit configured to generate a 5th signal by multiplexing the 3rd signal and the 4th signal.

Abstract: A semiconductor integrated circuit includes a clock recovery circuit that receive a multi-level pulse-amplitude modulated signal and to recover a clock signal. The clock recovery circuit includes a generation circuit and an oscillator. The generation circuit includes a plurality of comparators and pulse generators and a pulse summing circuit. The plurality of comparators and pulse generators compare the multi-level pulse-amplitude modulated signal with a plurality of threshold values to generate a plurality of pulses according to a plurality of comparison results. The pulse summing circuit generates a synthetic pulse based on the generated plurality of pulses. The oscillator oscillates in synchronization with the synthetic pulse to generate the clock signal.

Abstract: There is provided a case member having a structure for preventing the pushing-out of a seal member caused by gas leakage within a connector portion and also for preventing an annular lip portion of the seal member from falling when fitting the connector portion and a mating connector to each other. In the seal member 13, the annular lip portion 13f extends in a direction of connecting of the connector portion 18 to the mating connector in surrounding relation to electrical contact portions 19a of connection terminals 19. A seal member holder 15 is fitted on an outer peripheral surface of the connector portion 18. An annular groove 15f for receiving the annular lip portion 13f of the seal member 13 is formed in this seal member holder 15.

Abstract: A length of that portion of each of connection terminals 19 which projects from a partition wall 11a into a sealing member chamber 21, and includes an electrical contact portion 19a is larger than a length of an outer peripheral wall 11d of a connector portion 18, extending from the partition wall 11a in surrounding relation to the electrical contact portions 19a of the connection terminals 19 to form the sealing member chamber 21, so that at least distal end portions of the electrical contact portions 19a of the connection terminals 19 project outwardly from the connector portion 18 in a direction of fitting of the connector portion 18 to a mating connector 33.

Abstract: There is provided a case member having a structure for preventing the pushing-out of a seal member caused by gas leakage within a connector portion and also for preventing an annular lip portion of the seal member from falling when fitting the connector portion and a mating connector to each other. In the seal member 13, the annular lip portion 13f extends in a direction of connecting of the connector portion 18 to the mating connector in surrounding relation to electrical contact portions 19a of connection terminals 19. A seal member holder 15 is fitted on an outer peripheral surface of the connector portion 18. An annular groove 15f for receiving the annular lip portion 13f of the seal member 13 is formed in this seal member holder 15.

Abstract: A waterproof connector (100) receives female connection terminals (17) connected respectively to one ends of wires (21), and can be fitted to a mating connector (150) to be electrically connected thereto. The waterproof connector (100) includes an outer housing (11), an inner housing (13) which is provided within the outer housing (11), and holds the connection terminals (17) in such a manner that the inner housing is held in intimate contact with at least one of an outer peripheral surface of a wire press-fitting portion (17) of each connection terminal (17) and an outer peripheral surface of the associated wire (21), and a waterproof mechanism (15) which is made of a thermoplastic synthetic resin, and forms a liquid-tight seal between the wires (21), the outer housing (11) and the inner housing (13). The waterproof mechanism (15) is formed by the cured hot-melt adhesive.

Abstract: An electrical connector has a housing accommodating a plus signal terminal and a minus signal terminal. The connector housing also accommodates a first ground terminal corresponding to the plus signal terminal and a second ground terminal corresponding to the minus signal terminal. Each of the plus signal terminal, the minus signal terminal, the first ground terminal, and the second ground terminal is positioned at each corner of a quadrangle. A distance between the plus signal terminal and the first ground terminal is shorter than a distance between the minus signal terminal and the first ground terminal, while a distance between the minus signal terminal and the second ground terminal is shorter than a distance between the plus signal terminal and the second ground terminal. The connector may have a retainer body received in the connector housing for retaining the plus signal terminal, the minus signal terminal, the first ground terminal, and the second ground terminal.

Abstract: A waterproof structure between a cable and a housing is structured not spoiling a waterproof performance even if a cable is bent drawing a rapid curve. The waterproof structure between the cable and the housing comprises the cable led from the housing, a waterproof member closely attached to the housing and the cable, and a peel-prevention member for preventing peeling of the waterproof member with respect to the cable being bent, and is characterized in that the peel-prevention member is mounted on the cable and wrapped internally by the waterproof member. The waterproof member is formed with a hot melt material, and the peel-prevention member is formed with a material having excellent adhesion to the hot melt material. A shrinkage tube is served as the peel-prevention member.

Abstract: A waterproof connector 100 receives female connection terminals 17 connected respectively to one ends of wires 21, and can be fitted to a mating connector 150 to be electrically connected thereto. The waterproof connector 100 includes an outer housing 11, an inner housing 13 which is provided within the outer housing 11, and holds the connection terminals 17 in such a manner that the inner housing is held in intimate contact with at least one of an outer peripheral surface of a wire press-fitting portion 17 of each connection terminal 17 and an outer peripheral surface of the associated wire 21, and a waterproof mechanism 15 which is made of a thermoplastic synthetic resin, and forms a liquid-tight seal between the wires 21, the outer housing 11 and the inner housing 13. The waterproof mechanism 15 is formed by the cured hot-melt adhesive.