Abstract: A TDC circuit includes a plurality of delay elements connected in series. The TDC circuit includes a reference signal supply circuit that randomly selects one of the plurality of delay elements to supply a reference signal. The TDC circuit includes a plurality of latch circuits that latch a clock signal in response to outputs of the plurality of delay elements. The TDC circuit includes an output circuit that codes output signals output from the plurality of latch circuits and outputs a digital code indicating a relative time relationship of the clock signal with respect to the reference signal.

Abstract: According to one embodiment, a voltage-controlled oscillation (VCO) circuit includes a current source, an oscillation core unit, an amplitude detection unit, a current control unit, a low pass filter, and a switch. The current source supplies a bias current to the oscillation core unit in accordance with a current control signal. The oscillation core unit oscillates according to the bias current and outputs an oscillation signal. The amplitude detection unit outputs a detection voltage according to an amplitude of the oscillation signal. The current control unit outputs a control signal so that the detection voltage is equal to a reference voltage. The low pass filter generates the current control signal by filtering the control signal, and then supplies the current control signal to the current source. The switch is connected in parallel with the low pass filter.

Abstract: According to one embodiment, a voltage-controlled oscillation (VCO) circuit includes a current source, an oscillation core unit, an amplitude detection unit, a current control unit, a low pass filter, and a switch. The current source supplies a bias current to the oscillation core unit in accordance with a current control signal. The oscillation core unit oscillates according to the bias current and outputs an oscillation signal. The amplitude detection unit outputs a detection voltage according to an amplitude of the oscillation signal. The current control unit outputs a control signal so that the detection voltage is equal to a reference voltage. The low pass filter generates the current control signal by filtering the control signal, and then supplies the current control signal to the current source. The switch is connected in parallel with the low pass filter.

Abstract: An oscillation circuit including, a latch for generating an output signal based on a first signal and a second signal, an electric-charge charge/discharge unit which has first and second capacitors, and charges or discharges the first and second capacitors complementarily based on the output signal, a first comparator which compares a first voltage according to electric charge accumulated in the first capacitor and a first reference voltage, and outputs the first signal, a second comparator which compares a second voltage according to electric charge accumulated in the second capacitor and the first reference voltage, and outputs the second signal, and a control unit for controlling a timing, to compensate for variations of signals in the latch, the first comparator, and the second comparator, at which respective voltage levels of the first reference voltage and the first voltage match.

Abstract: An oscillation circuit includes an RS flip-flop for generating output signals based on a set signal and a reset signal, an electric-charge charge/discharge unit which has first and second capacitors and charges or discharges the first and second capacitors complementarily based on the output signals, a first comparator which compares a first voltage according to electric charge accumulated in the first capacitor and a first reference voltage and outputs the set signal, a second comparator which compares a second voltage according to electric charge accumulated in the second capacitor and the first reference voltage and outputs the reset signal, and a control unit for controlling a timing at which respective voltage levels of the first reference voltage and the first voltage match and a timing at which respective voltage levels of the first reference voltage and the second voltage match according to a frequency of the output signals.

Abstract: This invention provides an quadrature mixer which does not require a long time to adjust the amplitude value at the time of demodulation of the IQ signal. The quadrature mixer, comprising a first frequency-conversion unit that outputs a sixth signal derived by multiplying a first signal by a second and a fourth signals, a second frequency-conversion unit that outputs a seventh signal derived by multiplying the first signal by a third and a fifth signals, a first amplitude adjustment unit that outputs a eighth signal derived by multiplying the sixth signal by the third and fifth signals and a second amplitude adjustment unit that outputs a ninth signal derived by multiplying the seventh signal by the second and fifth signals.

Abstract: A digital phase comparator is provided in which first phase difference signals and second phase difference signals are used as digital phase difference information. The first phase difference signals are generated by sampling a second clock signal with a first group of clock signals having regular intervals. The second phase difference signals are generated, using a second group of clock signals and a first group of signals which are obtained by delaying a second clock signal and a first signal generated by performing a logic operation on the first phase difference signal respectively at different regular intervals, by sampling the second group of clock signals with the first group of signals.

Abstract: An oscillation circuit includes an RS flip-flop for generating output signals based on a set signal and a reset signal, an electric-charge charge/discharge unit which has first and second capacitors and charges or discharges the first and second capacitors complementarily based on the output signals, a first comparator which compares a first voltage according to electric charge accumulated in the first capacitor and a first reference voltage and outputs the set signal, a second comparator which compares a second voltage according to electric charge accumulated in the second capacitor and the first reference voltage and outputs the reset signal, and a control unit for controlling a timing at which respective voltage levels of the first reference voltage and the first voltage match and a timing at which respective voltage levels of the first reference voltage and the second voltage match according to a frequency of the output signals.

Abstract: This invention provides an quadrature mixer which does not require a long time to adjust the amplitude value at the time of demodulation of the IQ signal. The quadrature mixer, comprising a first frequency-conversion unit that outputs a sixth signal derived by multiplying a first signal by a second and a fourth signals, a second frequency-conversion unit that outputs a seventh signal derived by multiplying the first signal by a third and a fifth signals, a first amplitude adjustment unit that outputs a eighth signal derived by multiplying the sixth signal by the third and fifth signals and a second amplitude adjustment unit that outputs a ninth signal derived by multiplying the seventh signal by the second and fifth signals.

Abstract: A digital phase comparator is provided in which first phase difference signals and second phase difference signals are used as digital phase difference information. The first phase difference signals are generated by sampling a second clock signal with a first group of clock signals having regular intervals. The second phase difference signals are generated, using a second group of clock signals and a first group of signals which are obtained by delaying a second clock signal and a first signal generated by performing a logic operation on the first phase difference signal respectively at different regular intervals, by sampling the second group of clock signals with the first group of signals.

Abstract: A signal processing unit of the present invention includes: input terminal (21) to which an input signal is input; high-pass filter (23) for cutting off the DC component of the input signal; output terminal (22) for outputting a signal output from high-pass filter (23) as an output signal; determination element (26) for determining whether or not the voltage of the output signal falls out of a predetermined detection threshold range; and, switches (27,28) for connecting the output node of high-pass filter (23) to a power supply circuit when the voltage of the output signal is determined to fall out of the detection threshold range at determination element (26).

Abstract: A first frequency generator outputs a signal at first frequency f1 which satisfies a relationship of f1>f0 with desired frequency f0. A second frequency generator outputs a signal at second frequency f2 which satisfies a relationship of f2>f0 with desired frequency f0. A frequency discriminator frequency combines the signal generated from the first frequency generator with the signal generated from the second frequency generator to generate a signal which contains a component at desired frequency f0. The frequency discriminator further passes therethrough only a frequency region lower than a predetermined threshold frequency of the generated signal.

Abstract: A signal processing unit of the present invention includes: input terminal (21) to which an input signal is input; high-pass filter (23) for cutting off the DC component of the input signal; output terminal (22) for outputting a signal output from high-pass filter (23) as an output signal; determination element (26) for determining whether or not the voltage of the output signal falls out of a predetermined detection threshold range; and, switches (27,28) for connecting the output node of high-pass filter (23) to a power supply circuit when the voltage of the output signal is determined to fall out of the detection threshold range at determination element (26).

Abstract: For a balance adjustment due to a reduction in size and weight of an actuator, an arm portion, an axis attaching portion, and a coil supporting portion are arranged so that the centers of gravity on the coil side are located on a straight line connecting a rotational center and the center of gravity on the head side. Further, the improvement of an assembling efficiency of a VCM, an increase in torque, a one-touch fixing of an FPC connecting band, a noise prevention of a read pattern, and an insulation between the base and cover due to a bias of an MR read head are accomplished. A sector mark is detected by comparing a peak detection pulse and its reference polarity signal. A redundancy is provided to a reference detection polarity signal so that a read signal can be detected even if any one of the read signals of the sector marks is dropped out.

Abstract: A disk apparatus has a disk medium with sector areas that have a servo area and a data area along the same cylinder. The servo areas also have a sector mark indicative of the servo area, a code indicative of a cylinder address, and a predetermined servo pattern to detect a head position, all magnetically recorded in the servo area. A disk control section uses a head portion to detect the head position on the basis of a read signal of the servo pattern and positions the head portion at an arbitrary cylinder to perform reading and writing operations. The disk apparatus also has a time measuring counter for starting to measure an elapsed time each time a predetermined position in the servo area is detected, and a time setting register for storing a time from a detection time point of the predetermined position in the servo area to the generation of the sector pulse.

Abstract: For a balance adjustment due to a reduction in size and weight of an actuator, an arm portion, an axis attaching portion, and a coil supporting portion are arranged so that the centers of gravity on the coil side are located on a straight line connecting a rotational center and the center of gravity on the head side. Further, the improvement of an assembling efficiency of a VCM, an increase in torque, a one-touch fixing of an FPC connecting band, a noise prevention of a read pattern, and an insulation between the base and cover due to a bias of an MR read head are accomplished. A sector mark is detected by comparing a peak detection pulse and its reference polarity signal. A redundancy is provided to a reference detection polarity signal so that a read signal can be detected even if any one of the read signals of the sector marks is dropped out.