Abstract: Input logical data is sequentially divided by a data dividing circuit for each time slot into n data trains, of which each data block has an n time slot length. A clock signal which can be arbitrarily timed, is divided by a clock dividing circuit into a n clock signals which are displaced one time slot apart in phase and which occur with a period of n time slots. In a logical circuit, the divided clock signals are controlled by the divided data trains corresponding thereto, and the controlled clock signals are time multiplexed by a multiplexing circuit, whereby output data with which the input logical data has been timed by the clock signal is obtained.

Abstract: An address pattern generator for use in a test pattern generator for generating various patterns for testing semiconductor memories. A plurality of fixed registers for storing an initial value at the start of a test, a boundary value and an operand indicating the amount of change of an address are provided in common to at least two address operating circuits. The address operating circuits are each capable of taking therein the content of a desired one of the fixed registers. At least two output registers are provided, which are each capable of taking therein the operation result of a desired one of the address operating circuit. The contents of these output registers are supplied as addresses to a memory under test.

Abstract: A test pattern generating apparatus in which a microprogram describing a test pattern to be generated is read for interpretation and execution, address and data patterns are generated by arithmetic operations and a memory control signal is produced, the address and data patterns and the memory control signal being applied to a memory under test. The address pattern is provided to an area inversion control signal generation section to produce an inversion control signal corresponding to the address pattern, by which the data pattern may be inverted and then outputted.