Abstract: A bone-conduction loudspeaker set is provided which is similar to the form of a personal ornament. Systems suitable for this are also provided. The bone-conduction loudspeaker set includes: two bone-conduction loudspeaker units; and a loudspeaker-microphone switching unit which switches from a mode where the two bone-conduction loudspeaker units are used as right and left stereo loudspeakers to a mode where one of them is used as a loudspeaker and the other is used as a microphone, and vice versa. A system includes: a mutual-distance detection unit which detects the distance between the two bone-conduction loudspeaker units being within a predetermined distance; and a distress-signal issuance unit which issues a distress signal based on a detection result obtained by the mutual-distance detecting unit.

Abstract: A matched filter bank including a plurality of matched filters and a sampling and holding units commonly used by the total matched filters. Therefore, the circuit size is diminished. An inverting amplifier for the matched filter with a variable gain includes an input capacitance, an inverting amplifier connected to an output of the input capacitance, and a plurality of feedback capacitances connected between an input and output of the inverting amplifier. A plurality of switches are connected to input side of the feedback capacitances for alternatively connecting the feedback capcitanec to the input of the inverting amplifier or a reference voltage. The feedback capacitances connected to the reference voltage are invalid with respect to a composite capacitance of the feedback capacitance and have no influence to the amplifier.

Abstract: An analog to digital converter comprises a differential input portion that receives an input voltage and a reference voltage and has a first and second output terminals, a positive feedback portion connected to said first and second output terminals, a buffer if CMOSFETs connected at its input to the first output terminal, a second buffer connected at its input to the second output terminal, and a comparison circuit including a first switching portion connected between the first and second output terminals for connecting and disconnecting the first and second output terminals in response to a comparison clock signal. The comparison circuit is connected at its output to the first or second buffer. The input voltage and the reference voltage are compared when said switching portion changes from the connecting condition to the disconnecting condition in response to the comparison clock signal.

Abstract: A filter circuit comprises a plurality of sampling and holding circuits for sampling and holding analog input signal with a predetermined sampling period, a calculation circuit for multiplying each the analog input signal by a predetermined multiplier, and for summing the multiplication results. The sampling and holding circuits are controlled in an electrical power such that the electrical power is decreased when holding.

Abstract: An A/D converter having a plurality of thresholding circuits corresponding to bits of output digital data, each of which includes odd number of inverters serially connected from a first stage to a last stage. The first stage inverter of the thresholding circuits have thresholds equal to a weights of the bits. The inverters of the last stage are of thresholds different from those of the first stage.

Abstract: A computational circuit for a multi-value addition comprising a parallel adder, an output adder, a quantizing portion and a logic conversion portion. Addition circuits in the above adders and thresholding circuits in the above quantizing portion consist of voltage-driven circuits including capacitive couplings.

Abstract: An inverting amplifying circuit for outputting an inversion of an input with good linearity, having an inverter circuit, a feedback capacitance, an input capacitance, a first refresh switch, a second refresh switch, a sleep switch, and a first cutoff switch. A sleep voltage is input through the sleep switch to the inverter circuit for minimizing the electrical power consumption. The sleep switch connects a terminal of the inverter circuit directly to ground when in a sleep mode. The first cut off switch is connected between an output of the inverter circuit and an output of the inverting amplifying circuit.

Abstract: An stable inverted amplifying circuit includes an odd number of CMOS inverters and a feedback capacitance. Balancing resistances decrease the inverter open gain and limit the gain of the entire circuit. Serial capacitances act to prevent low-frequency oscillation. Oscillation-preventing circuits are also provided to reduce high-frequency oscillation. Sleep, refresh, and sleep-refresh switches are used to cancel residual loads and reduce power consumption.

Abstract: An operational amplifier is equipped at its input stage with a folded cascode type differential amplifier and at its downstream stage with pre-buffers, which include a differential amplification stage of PMOS input and a differential amplification stage of NMOS input, as level shifters. A MOS resistor having its gate terminal fed with an intermediate bias potential between a supply voltage V.sub.DD and an earth potential is connected between every one of the drain terminals of current-mirror connected load MOSFETs in the pre-buffers. As a result, the gains of the pre-buffers in the steady state can be suppressed to about 10 dB or less. The individual MOSFETs of the push-pull output stage are individually driven by the pre-buffers of low gains.