Patents by Inventor Takashi TONOKAWA
Takashi TONOKAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220123358Abstract: A technique of improving the performance of a secondary battery is provided. A secondary battery according to an embodiment includes a first electrode, a second electrode, a first layer disposed on the first electrode and including a first n-type oxide semiconductor, a second layer disposed on the first layer and including a second n-type oxide semiconductor material and a first insulating material, a third layer which is disposed on the second layer and is a solid electrolyte layer, and a fourth layer disposed on the third layer and including hexagonal Ni(OH)2 microcrystals.Type: ApplicationFiled: January 30, 2020Publication date: April 21, 2022Inventors: Kazuyuki TSUNOKUNI, Juri OGASAWARA, Takashi TONOKAWA, Hiroyuki KATO
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Patent number: 11245113Abstract: A secondary battery includes: a first oxide semiconductor having a first conductivity type; a first charging layer disposed on the first oxide semiconductor layer, and composed by including a first insulating material and a second oxide semiconductor having the first conductivity type; a second charging layer disposed on the first charging layer; a third oxide semiconductor layer having a second conductivity type disposed on the second charging layer; and a hydroxide layer disposed between the first charging layer and the third oxide semiconductor layer, and containing a hydroxide of a metal constituting the third oxide semiconductor layer. The highly reliable secondary battery is capable of improving an energy density and increasing battery characteristics (electricity accumulation capacity).Type: GrantFiled: February 26, 2019Date of Patent: February 8, 2022Assignee: Kabushiki Kaisha Nihon MicronicsInventors: Takashi Tonokawa, Yutaka Kosaka, Kazuyuki Tsunokuni, Hikaru Takano, Shigefusa Chichibu, Kazunobu Kojima
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Patent number: 10991933Abstract: A secondary battery according to the present invention includes a first electrode, a second electrode, a charging layer arranged between the first electrode (11) and the second electrode and containing a mixture of an insulating material and a first n-type oxide semiconductor material, an n-type oxide semiconductor layer arranged between the charging layer and the first electrode and containing a second n-type oxide semiconductor material, a p-type oxide semiconductor layer (16) arranged between the charging layer and the second electrode and containing a p-type oxide semiconductor material, a mixture layer arranged between the charging layer and the p-type oxide semiconductor layer and containing a mixture of silicon oxide and a third n-type oxide semiconductor material, and a conductive layer arranged between the first electrode and the n-type oxide semiconductor layer and containing a metal material.Type: GrantFiled: July 21, 2017Date of Patent: April 27, 2021Assignee: KABUSHIKI KAISHA NIHON MICRONICSInventors: Takuo Kudoh, Harutada Dewa, Hikaru Takano, Tomokazu Saito, Takashi Tonokawa
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Publication number: 20200373575Abstract: A secondary battery includes: a solid electrolyte layer including at least one of water (H2O) and a hydroxyl group (—OH); a positive-electrode active material layer disposed on the solid electrolyte layer and including nickel hydroxide; a second electrode (positive electrode) disposed on the positive-electrode active material layer; a negative-electrode active material layer disposed on a lower surface of the solid electrolyte layer so as to be opposite to the positive-electrode active material layer, and including a titanium oxide compound (TiOx) including at least one of water and a hydroxyl group; a first electrode (negative electrode) disposed on a lower surface of the negative-electrode active material layer so as to be opposite to the second electrode; a p type semiconductor layer disposed between the positive-electrode active material layer and the second electrode; and an n type semiconductor layer disposed between the negative-electrode active material layer and the first electrode.Type: ApplicationFiled: August 12, 2020Publication date: November 26, 2020Inventors: Kazuyuki TSUNOKUNI, Takashi TONOKAWA, Kunihiko NAKADA, Yutaka KOSAKA
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Patent number: 10686210Abstract: A method for manufacturing oxide semiconductor secondary cells concurrently and evenly on a plurality of chips. A method for manufacturing a chip on which an oxide semiconductor secondary cell is mounted, the oxide semiconductor secondary cell that is formed by layering a first electrode, a charging function layer, and a second electrode being layered on a circuit. The method includes a layering process to layer and form the oxide semiconductor secondary cells integrally at regions corresponding to a plurality of chips formed on a wafer without separately forming oxide semiconductor secondary cells at regions corresponding to the respective chips, and a separating process to perform separation into individual oxide semiconductor secondary cells corresponding to the respective chips by performing pattern etching on the integrally-formed oxide semiconductor secondary cells to eliminate regions not corresponding to the respective chips except for regions corresponding to the respective chips.Type: GrantFiled: June 20, 2016Date of Patent: June 16, 2020Assignee: KABUSHIKI KAISHA NIHON MICRONICSInventors: Kazuyuki Tsunokuni, Tatsuo Inoue, Tomokazu Saitoh, Juri Ogasawara, Takashi Tonokawa, Takuo Kudoh
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Publication number: 20200185701Abstract: A secondary battery according to the present invention includes a first electrode, a second electrode, a charging layer arranged between the first electrode (11) and the second electrode and containing a mixture of an insulating material and a first n-type oxide semiconductor material, an n-type oxide semiconductor layer arranged between the charging layer and the first electrode and containing a second n-type oxide semiconductor material, a p-type oxide semiconductor layer (16) arranged between the charging layer and the second electrode and containing a p-type oxide semiconductor material, a mixture layer arranged between the charging layer and the p-type oxide semiconductor layer and containing a mixture of silicon oxide and a third n-type oxide semiconductor material, and a conductive layer arranged between the first electrode and the n-type oxide semiconductor layer and containing a metal material.Type: ApplicationFiled: July 21, 2017Publication date: June 11, 2020Inventors: Takuo KUDOH, Harutada DEWA, Hikaru TAKANO, Tomokazu SAITO, Takashi TONOKAWA
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Publication number: 20200006763Abstract: The electricity storage device includes: a first oxide semiconductor layer having a first conductivity-type first oxide semiconductor; a first charge layer disposed on the first oxide semiconductor layer, and composed by including a first insulating material and a first conductivity-type second oxide semiconductor; and a third oxide semiconductor layer disposed on the first charge layer. The third oxide semiconductor layer has hydrogen and a second conductivity-type third oxide semiconductor, and a percentage of the hydrogen with respect to a metal constituting the third oxide semiconductor is equal to or greater than 40%. The embodiments provide an electricity storage device capable of increasing an electricity storage capacity per unit volume (weight).Type: ApplicationFiled: September 12, 2019Publication date: January 2, 2020Inventors: Takashi TONOKAWA, Kazuyuki TSUNOKUNI, Takuo KUDOH
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Publication number: 20200006009Abstract: The electricity storage device includes: a first conductivity-type first oxide semiconductor; a solid electrolyte layer disposed on the first oxide semiconductor layer, the solid electrolyte layer including a solid electrolyte enabling proton movement; an insulator layer disposed between the solid electrolyte layer and the first oxide semiconductor layer, the insulator layer including an insulating material; and a second conductivity-type second oxide semiconductor layer disposed on the solid electrolyte layer. Provided is the electricity storage device having the increased electricity storage capacity and improved reliability that can be charged without degradation even when the charging voltage is increased.Type: ApplicationFiled: September 12, 2019Publication date: January 2, 2020Inventors: Takashi TONOKAWA, Kazuyuki TSUNOKUNI, Juri OGASAWARA, Yuki SATO
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Publication number: 20190190024Abstract: A secondary battery includes: a first oxide semiconductor having a first conductivity type; a first charging layer disposed on the first oxide semiconductor layer, and composed by including a first insulating material and a second oxide semiconductor having the first conductivity type; a second charging layer disposed on the first charging layer; a third oxide semiconductor layer having a second conductivity type disposed on the second charging layer; and a hydroxide layer disposed between the first charging layer and the third oxide semiconductor layer, and containing a hydroxide of a metal constituting the third oxide semiconductor layer. The highly reliable secondary battery is capable of improving an energy density and increasing battery characteristics (electricity accumulation capacity).Type: ApplicationFiled: February 26, 2019Publication date: June 20, 2019Inventors: Takashi TONOKAWA, Yutaka KOSAKA, Kazuyuki TSUNOKUNI, Hikaru TAKANO, Shigefusa CHICHIBU, Kazunobu KOJIMA
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Patent number: 10090507Abstract: A secondary battery-mounted circuit chip wherein secondary battery is directly fabricated on opposed surface of formed circuit into an integrated structure of the secondary battery and circuit, and a manufacturing method thereof. Secondary battery-mounted circuit chip is configured such that secondary battery is directly fabricated in region corresponding to circuit into integrated structure of secondary battery and circuit. The chip is secondary battery-mounted circuit chip wherein secondary battery is formed on surface opposing a circuit region fabricated on wafer.Type: GrantFiled: March 5, 2014Date of Patent: October 2, 2018Assignees: KABUSHIKI KAISHA NIHON MICRONICS, GUALA TECHNOLOGY CO., LTD.Inventors: Kazuyuki Tsunokuni, Tatsuo Inoue, Kiyoyasu Hiwada, Takashi Tonokawa, Akira Nakazawa
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Publication number: 20180226674Abstract: A method for manufacturing oxide semiconductor secondary cells concurrently and evenly on a plurality of chips. A method for manufacturing a chip on which an oxide semiconductor secondary cell is mounted, the oxide semiconductor secondary cell that is formed by layering a first electrode, a charging function layer, and a second electrode being layered on a circuit. The method includes a layering process to layer and form the oxide semiconductor secondary cells integrally at regions corresponding to a plurality of chips formed on a wafer without separately forming oxide semiconductor secondary cells at regions corresponding to the respective chips, and a separating process to perform separation into individual oxide semiconductor secondary cells corresponding to the respective chips by performing pattern etching on the integrally-formed oxide semiconductor secondary cells to eliminate regions not corresponding to the respective chips except for regions corresponding to the respective chips.Type: ApplicationFiled: June 20, 2016Publication date: August 9, 2018Applicant: KABUSHIKI KAISHA NIHON MICRONICSInventors: Kazuyuki TSUNOKUNI, Tatsuo INOUE, Tomokazu SAITOH, Juri OGASAWARA, Takashi TONOKAWA, Takuo KUDOH
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Publication number: 20160181588Abstract: A secondary battery-mounted circuit chip wherein secondary battery is directly fabricated on opposed surface of formed circuit into an integrated structure of the secondary battery and circuit, and a manufacturing method thereof. Secondary battery-mounted circuit chip is configured such that secondary battery is directly fabricated in region corresponding to circuit into integrated structure of secondary battery and circuit. The chip is secondary battery-mounted circuit chip wherein secondary battery is formed on surface opposing a circuit region fabricated on wafer.Type: ApplicationFiled: March 5, 2014Publication date: June 23, 2016Inventors: Kazuyuki TSUNOKUNI, Tatsuo INOUE, Kiyoyasu HIWADA, Takashi TONOKAWA, Akira NAKAZAWA