Abstract: A horizontal synchronizing signal is applied as a reference signal and a voltage-controlled oscillator outputs a display clock signal on the basis of the frequency of the horizontal synchronizing signal. The frequency of the display clock signal is frequency-divided in accordance with a frequency-dividing value selected from among a plurality of frequency-dividing signals stored in advance, the difference in frequency between the frequency-divided display clock signal and the horizontal synchronizing signal and the phase difference between them are obtained by a phase comparator, and the frequency of the signal outputted by the voltage-controlled oscillator is decided in dependence upon the frequency difference. In an interval in which a vertical synchronizing signal turns off and the frequency of the horizontal synchronizing signal fluctuates, the reference signal and the horizontal synchronizing signal input to the phase comparator are held fixed to prevent a fluctuation in the outputted display clock.

Abstract: Disclosed is a method for producing aromatic hydrocarbons, which comprises contacting a light hydrocarbon feedstock comprising olefins and/or paraffins with a zeolite catalyst in a fixed-bed, adiabatic reactor containing a fixed catalyst bed comprised of the zeolite catalyst, to thereby effect a catalytic cyclization reaction of the light hydrocarbon feedstock, wherein the catalytic cyclization reaction is performed under conditions which satisfy the following requirements: (1) the zeolite catalyst has an initial stage-catalytic activity of 0.2 (sec.sup.-1) or more in terms of the initial stage, first-order reaction rate constant of the decomposition of n-hexane catalyzed by the zeolite catalyst; (2) the catalyst bed has a temperature of from 450.degree. C. to 650.degree. C.

Abstract: A method for partially dealuminating a zeolite catalyst by steaming, which comprises feeding steam to and flowing the steam through a reactor containing a catalyst bed of a zeolite catalyst to contact the zeolite catalyst with the steam for 0.1 to 50 hours under temperature distribution conditions which satisfies the following requirements (1) and (2):(1) 500.degree. C..ltoreq.T.sub.0 .ltoreq.T.ltoreq.T.sub.2 .ltoreq.700.degree. C. wherein T.sub.0 is the temperature (.degree.C.) of the fed steam; T.sub.2 is the maximum temperature (.degree.C.) of the catalyst bed; and T is the average temperature (.degree.C.) of the catalyst bed, which is defined by the formula: ##EQU1## wherein T.sub.i is the time average temperature (.degree.C.) of the i-th block of n equilength blocks of the catalyst bed, which are arranged along the direction of steam flow; and(2) cv(T).times.1000.ltoreq.

Abstract: A horizontal synchronizing signal is applied as a reference signal and a voltage-controlled oscillator outputs a frequency signal on the basis of the frequency of the horizontal synchronizing signal. The period of the frequency signal is divided in accordance with a frequency-dividing value set in advance, the difference in frequency between the frequency-divided frequency signal and the horizontal synchronizing signal and the phase difference between them are obtained, and control is performed in such a manner that the frequency of the signal outputted by the voltage-controlled oscillator is decided in dependence upon the frequency difference. In an interval in which a vertical synchronizing signal turns off and the frequency of the horizontal synchronizing signal fluctuates, the input to the voltage-controlled oscillator is held fixed to prevent a fluctuation in the outputted display clock.

Abstract: In a video display control, a phase locked loop (PLL) circuit generates a multiplied frequency signal from a reference signal. The stability of the PLL circuit is maintained even when the reference signal has different frequencies by providing a number of multiplication values corresponding to the number of different reference signal frequencies and switching the multiplication value when a change in frequency is detected to stabilize the PLL circuit.

Abstract: A minimum number of clock pulses required for keeping an electronic component in a waiting condition or state are intermittently applied to the electronic component, thereby minimizing the heat dissipation thereof. A control circuit, utilized in the invention, provides an output signal which permits continuous clock signals to be applied, for example, to memory chips, during read and write periods, but such control circuit reduces the number of clock signals applied to the memory chips during periods when the read and write processes are not required.