Patents by Inventor Takashi Tsurugai

Takashi Tsurugai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11847389
    Abstract: An optimization device includes an output data acquisitor that acquires output data having a second number of dimensions obtained by performing an experiment or a simulation, an evaluation value calculator that calculates and outputs an evaluation value of the output data, a features extractor that extracts an output data features having a third number of dimensions different from the second number of dimensions, an input parameter converter that generates a conversion parameter related to the output data features predicted from the input parameters, a next input parameter determinator that determines a next input parameter to be acquired by the output data acquisitor, based on the conversion parameter and the corresponding evaluation value, and an iterative determinator that repeats processes of the output data acquisitor, the input/output data storage, the evaluation value calculator, the features extractor, the input parameter converter, and the next input parameter determinator.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: December 19, 2023
    Assignees: Kioxia Corporation, KABUSHIKI KAISHA TOSHIBA
    Inventors: Satoru Yokota, Daiki Kiribuchi, Takeichiro Nishikawa, Soh Koike, Takashi Tsurugai
  • Publication number: 20210248293
    Abstract: An optimization device includes an output data acquisitor that acquires output data having a second number of dimensions obtained by performing an experiment or a simulation, an evaluation value calculator that calculates and outputs an evaluation value of the output data, a features extractor that extracts an output data features having a third number of dimensions different from the second number of dimensions, an input parameter converter that generates a conversion parameter related to the output data features predicted from the input parameters, a next input parameter determinator that determines a next input parameter to be acquired by the output data acquisitor, based on the conversion parameter and the corresponding evaluation value, and an iterative determinator that repeats processes of the output data acquisitor, the input/output data storage, the evaluation value calculator, the features extractor, the input parameter converter, and the next input parameter determinator.
    Type: Application
    Filed: September 8, 2020
    Publication date: August 12, 2021
    Applicants: Kioxia Corporation, KABUSHIKI KAISHA TOSHIBA
    Inventors: Satoru YOKOTA, Daiki KIRIBUCHI, Takeichiro NISHIKAWA, Soh KOIKE, Takashi TSURUGAI
  • Patent number: 8362554
    Abstract: According to one embodiment, a semiconductor device includes a drain region, a source region, a channel region, an insulating film, a gate electrode, a first semiconductor region, and a second semiconductor region. The source region includes a source layer of the first conductivity type, a first back gate layer of the second conductivity type, and a second back gate layer of the second conductivity type. The first back gate layer is adjacent to the second semiconductor region on one side in a channel length direction, and is adjacent to the source layer on one other side in the channel length direction. The second back gate layer is adjacent to the source layer on the one side in the channel length direction, and is adjacent to the second semiconductor region on the one other side in the channel length direction.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: January 29, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoko Matsudai, Norio Yasuhara, Takashi Tsurugai, Kumiko Sato
  • Publication number: 20110095369
    Abstract: According to one embodiment, a semiconductor device includes a drain region, a source region, a channel region, an insulating film, a gate electrode, a first semiconductor region, and a second semiconductor region. The source region includes a source layer of the first conductivity type, a first back gate layer of the second conductivity type, and a second back gate layer of the second conductivity type. The first back gate layer is adjacent to the second semiconductor region on one side in a channel length direction, and is adjacent to the source layer on one other side in the channel length direction. The second back gate layer is adjacent to the source layer on the one side in the channel length direction, and is adjacent to the second semiconductor region on the one other side in the channel length direction.
    Type: Application
    Filed: September 9, 2010
    Publication date: April 28, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tomoko Matsudai, Norio Yasuhara, Takashi Tsurugai, Kumiko Sato