Patents by Inventor Takashi Uchino
Takashi Uchino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7064454Abstract: A power generator system incorporates a generator driven by an engine. A case houses the generator and the engine. A controller communicates with the engine so as to control the speed at which the engine drives the generator. A temperature sensor is disposed so as to sense a temperature within the case and to send a temperature signal to the controller. The controller controls the speed of the engine depending upon at least the temperature signal received from the temperature sensor.Type: GrantFiled: April 16, 2003Date of Patent: June 20, 2006Assignee: Yamaha Hatsudoki Kabushiki KaishaInventors: Mitsuo Fukaya, Takashi Uchino, Takahide Sugiyama
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Publication number: 20050101097Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.Type: ApplicationFiled: December 1, 2004Publication date: May 12, 2005Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
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Publication number: 20050034483Abstract: According to the present invention, there is provided a method for manufacturing silica glass of a bulk state as dense as conventional fused silica by a low-temperature process. Fumed silica particles are produced by oxidizing and hydrolyzing SiCl4 gas with a flame of 1100-1400° C. which is obtained by burning mixed gas of H2 and O2. Such fumed silica particles are used as a raw material, and pressure is applied to the aggregate of the fumed silica particles so as to unite the particles with respect to each other.Type: ApplicationFiled: October 25, 2002Publication date: February 17, 2005Inventors: Koichi Sakaguchi, Toshinobu Yoko, Takashi Uchino, Akifumi Sakoh
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Patent number: 6835632Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.Type: GrantFiled: June 13, 2003Date of Patent: December 28, 2004Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
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Patent number: 6781202Abstract: A higher-performance short channel MOS transistor with enhanced resistance to soft errors caused by exposure to high-energy rays is realized. At the time of forming a deep source/drain diffusion layer region at high density, an intermediate region of a density higher than that of impurity of a semiconductor substrate is formed between the source/drain diffusion layer and the semiconductor substrate of a conduction type opposite to that of the source/drain diffusion layer. The intermediate region is formed with a diffusion window for forming the source/drain, an intermediate layer of uniform concentration and uniform width can be realized at low cost.Type: GrantFiled: November 26, 2002Date of Patent: August 24, 2004Assignee: Hitachi, Ltd.Inventors: Ken Yamaguchi, Yoshiaki Takemura, Kenichi Osada, Masatada Horiuchi, Takashi Uchino
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Publication number: 20030209909Abstract: A power generator system incorporates a generator driven by an engine. A case houses the generator and the engine. A controller communicates with the engine so as to control the speed at which the engine drives the generator. A temperature sensor is disposed so as to sense a temperature within the case and to send a temperature signal to the controller. The controller controls the speed of the engine depending upon at least the temperature signal received from the temperature sensor.Type: ApplicationFiled: April 16, 2003Publication date: November 13, 2003Inventors: Mitsuo Fukaya, Takashi Uchino, Takahide Sugiyama
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Publication number: 20030207544Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.Type: ApplicationFiled: June 13, 2003Publication date: November 6, 2003Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
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Patent number: 6610569Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the polycrystalline first silicon layer has a positive in temperature dependence of resist while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.Type: GrantFiled: August 28, 2000Date of Patent: August 26, 2003Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
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Publication number: 20030137012Abstract: A higher-performance short channel MOS transistor with enhanced resistance to soft errors caused by exposure to high-energy rays is realized. At the time of forming a deep source/drain diffusion layer region at high density, an intermediate region of a density higher than that of impurity of a semiconductor substrate is formed between the source/drain diffusion layer and the semiconductor substrate of a conduction type opposite to that of the source/drain diffusion layer. The intermediate region is formed with a diffusion window for forming the source/drain, an intermediate layer of uniform concentration and uniform width can be realized at low cost.Type: ApplicationFiled: November 26, 2002Publication date: July 24, 2003Inventors: Ken Yamaguchi, Yoshiaki Takemura, Kenichi Osada, Masatada Horiuchi, Takashi Uchino
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Patent number: 6524924Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistances while the second polycrystalline layer has a negative temperature dependance of resistance, or vise versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.Type: GrantFiled: July 28, 1998Date of Patent: February 25, 2003Assignees: Hitachi, Ltd., Hitachi Device EngineeringInventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
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Publication number: 20010026624Abstract: Volume adjustment is performed in small steps at a DSP (12) and volume adjustment is performed in wide steps at electronic volume circuits (18L, 18R). Adjustment only by the DSP (12) is performed for a small volume range less than or equal to a predetermined level. For a volume higher than or equal to the predetermined level, fine adjustment by the DSP (12) at the transient period of volume adjustment is combined to reduce the increment of variation so that the volume adjustment is performed gradually.Type: ApplicationFiled: March 26, 2001Publication date: October 4, 2001Inventors: Yoshihiko Kon, Takashi Uchino, Hiroshi Kaneko, Takahiko Masumoto
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Patent number: 6133094Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.Type: GrantFiled: July 28, 1998Date of Patent: October 17, 2000Assignees: Hitachi Ltd, Hitachi Device Engineering Co.Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
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Patent number: 6017836Abstract: Ultraviolet and infrared radiation absorbing glass comprising, as basic glass components, 65 to 80% by weight of SiO.sub.2, 0 to 5% by weight of Al.sub.2 O.sub.3, 0 to 10% by weight of MgO, 5 to 15% by weight of CaO, 10 to 18% by weight of Na.sub.2 O, 0 to 5% by weight of K.sub.2 O, 5 to 15% by weight in total of MgO and CaO, 10 to 20% by weight in total of Na.sub.2 O and K.sub.2 O, and 0.2 to 5.0% by weight of B.sub.2 O.sub.3 ; and as coloring components, 0.5 to 1.0% by weight, in terms of Fe.sub.2 O.sub.3, of total iron oxide having a ratio of FeO based on the total iron oxide of 0.20 to 0.40, 0.2 to 2.0% by weight of CeO.sub.2, and 0 to 1.0% by weight of TiO.sub.2, and ultraviolet and infrared radiation absorbing glass comprising, as basic glass components, 65 to 80% by weight of SiO.sub.2, 0 to 5% by weight of Al.sub.2 O.sub.3, 0 to 10% by weight of MgO, 5 to 15% by weight of CaO, 10 to 18% by weight of Na.sub.2 O, 0 to 5% by weight of K.sub.Type: GrantFiled: June 3, 1996Date of Patent: January 25, 2000Assignee: Nippon Sheet Glass Co., Ltd.Inventors: Yukihito Nagashima, Koichi Sakaguchi, Takashi Uchino
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Patent number: 5793097Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.Type: GrantFiled: August 24, 1995Date of Patent: August 11, 1998Assignees: Hitachi, Ltd., Hitachi Device Engineering Company, Ltd.Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
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Patent number: 5773340Abstract: A method of manufacturing an improved bipolar transistor or BiCMOS having a phosphorus-doped polysilicon emitter electrode is disclosed. The method comprises forming an emitter electrode wherein a phosphorus-doped amorphous silicon film is deposited at temperature not higher than 540.degree. C. and then subjected to low temperature annealing treatment at a temperature of 600.degree. C. to 750.degree. C., under which the amorphous silicon is converted to a polysilicon and the phosphorus present in the amorphous silicon film is diffused into a base region to form an emitter region, followed by high temperature/short time annealing treatment at a temperature of 900.degree. C. to 950.degree. C. so that an activation rate of an impurity in a boron-doped polysilicon base electrode or source-drain regions of MOS.cndot.FET is improved.Type: GrantFiled: November 28, 1995Date of Patent: June 30, 1998Assignee: Hitachi, Ltd.Inventors: Takahiro Kumauchi, Takashi Hashimoto, Osamu Kasahara, Satoshi Yamamoto, Yoichi Tamaki, Takeo Shiba, Takashi Uchino
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Patent number: 5768187Abstract: This non-volatile multi-state memory device switches a storing resolution of multi-state data corresponding to digital data stored in a non-volatile memory cell according to the data's characteristics. In more detail, digital audio data are output from an ADPCM encoder in n-bit units and m bits of address data indicating an address at which audio data are stored are output from an address controller. These are then input to a switching circuit, a bit number converting circuit converts m bits of address data to n bits of address data at the same level as the m bit data, and the converted n bits of address data and n bits of audio data are inputted to a second multiplexer. An output of the Second multiplexer is then selected in compliance with a switch signal from the address controller and either the selected n bits of address data or the audio data are sent to a read-write circuit.Type: GrantFiled: September 25, 1996Date of Patent: June 16, 1998Assignee: Sanyo Electric Co., Ltd.Inventors: Takashi Uchino, Nozomu Nambu, Akio Hagiwara
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Patent number: 5761117Abstract: Inputted digital data are held in a data register and converted to multi-state analog amount by a resistance dividing circuit and a decoder. A comparator compares an analog amount read from a non-volatile memory cell with a converted analog amount; and in accordance with this comparison result, a writing voltage is supplied to a memory cell. A first bias generating circuit is provided for generating two different types of bias voltages as this writing voltage, MOS transistors are inserted as respective switches to the bias voltage supply lines and writing voltages are switched by selectively ON/OFF-controlling one of the MOS transistors in accordance with the upper bit of the inputted digital data. As a result, unnecessary writing time can be eliminated, time required for executing writing can be reduced and circuit configuration can be simplified.Type: GrantFiled: August 29, 1996Date of Patent: June 2, 1998Assignee: Sanyo Electric Co., Ltd.Inventors: Takashi Uchino, Nozomu Nambu, Akio Hagiwara
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Patent number: 5625584Abstract: A data register for holding input digital data, a resistance dividing circuit for generating a plurality of analog voltages, a decoder for decoding the data of the data register and selectively outputting one of a plurality of analog voltages and a comparator for comparing this decoded output with an analog amount read from a memory cell are provided. In write mode, this memory device sets data to be written in the data register and writes an analog amount corresponding to the set data in the memory cell, in read mode, the apparatus sequentially sets in the data register digital data updated in sequence from a designated value, executes comparison at the comparator for each setting and terminates the digital data setting in response to the comparison result at the data register, thus digital data corresponding to the analog amount read from the memory cell is thereby obtained at the data register. As a result, circuit configuration can be simplified and circuit scale reduced.Type: GrantFiled: August 30, 1996Date of Patent: April 29, 1997Assignee: Sanyo Electric Co., Ltd.Inventors: Takashi Uchino, Nozomu Nambu, Akio Hagiwara
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Patent number: 5424575Abstract: A semiconductor device has an electrically insulating substrate and a semiconductor layer formed on the insulating substrate. A plurality of semiconductor regions are defined so as to be joined to each other to form at least two homojunctions in the semiconductor layer. A lead conductor for one of the semiconductor regions which is required to have a small thickness has a specific structure such that the lead conductor is in contact with the one semiconductor region at the main surface of the semiconductor layer for electrical connection therebetween and extends over that portion of the semiconductor layer which contributes to definition of at least one of the semiconductor regions other than the first-mentioned one semiconductor region.Type: GrantFiled: June 1, 1992Date of Patent: June 13, 1995Assignee: Hitachi, Ltd.Inventors: Katsuyoshi Washio, Tohru Nakamura, Takahiro Onai, Masatada Horiuchi, Takashi Uchino