Patents by Inventor Takashi Utsumi
Takashi Utsumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20110147376Abstract: A cooking device comprises: a heating chamber (11) equipped with a placement section (11d), the placement section (11d) being adapted such that a tray (17) is placed thereon, the tray (17) having a placement net (17a) for placing thereon an object to be cooked; a vapor generating device (1) for generating vapor and supplying the vapor between the placement net (17a) and the tray (17); a circulation duct (12) having a circulation fan (16) and circulating gas in the heating chamber (11); a convection heater (15) provided in the circulation duct (12); a gas supply opening (38) provided below the tray (17); a gas discharge opening (41) provided below the tray (17); and a magnetron (33) for supplying a microwave to the heating chamber (11).Type: ApplicationFiled: August 28, 2009Publication date: June 23, 2011Inventors: Shinya Ueda, Hideo Shimoda, Takashi Utsumi
-
Publication number: 20110095013Abstract: A steam generating device (1) is provided with a metal housing (2), a water supply opening (3) for supplying water into the housing (2), a steam generating heater (4) embedded in the lower part of the housing (2) and evaporating the water supplied from the water supply opening (3), a steam temperature raising heater (5) provided above the steam generating heater (4) with a predetermined distance from an inner wall of the housing (2) and raising the temperature of the steam generated by the steam generating heater (4), and a discharge opening (8) for discharging the superheated steam generated by the steam temperature raising heater (5).Type: ApplicationFiled: June 24, 2009Publication date: April 28, 2011Inventors: Takashi Utsumi, Hideo Shimoda, Shinya Ueda, Yasuhiro Sakoda
-
Patent number: 7269924Abstract: A device and method of notifying operation of a vehicle closure member is disclosed having a door drive motor 9 for driving a vehicle closure member, mounted in a vehicle, between an open position and a closed position, a pulse encoder 6 detecting a closure position of the vehicle closure member, and a notifying unit 7 notifying a user of operation of the vehicle closure member, with control being executed to apply a motor brake on the vehicle closure member at a time instant t1, upon recognition of operation for reverse movement when the closure position detected with the pulse encoder 9 remains in an area-just-prior-to-fully-closed-position between a half-latch position and the open position, whereupon a buzzer is activated at a time instant t2 with the motor brake being terminated when the vehicle closure member remains in the area-just-prior-to-fully-closed-position.Type: GrantFiled: October 5, 2005Date of Patent: September 18, 2007Assignees: Nissan Motor Co., Ltd., Keihin Corporation, Nippon Cable System, Inc.Inventors: Noboru Otomo, Hitoshi Kidokoro, Yoichi Koga, Takashi Sanda, Takashi Utsumi
-
Publication number: 20060170988Abstract: A film carrier conveys photographic film along a conveyance path to an image reading position, in order to read an image by irradiating with light an image frame recorded in the photographic film. The film carrier includes: a reference plate for setting the photographic film at a reference position; a pair of mask members that press and release both conveyance-direction edge portions of the surface of the photographic film conveyed to the image reading position; mask member moving unit that causes the pair of mask members to move along the conveyance direction in accordance with the size of the image frame; a pair of pressure members that nip and release the photographic film; and pressure member moving unit that causes the pair of pressure members to move toward and away from the reference plate.Type: ApplicationFiled: December 5, 2005Publication date: August 3, 2006Inventors: Kenichi Kato, Hisatsugu Torii, Yoshiyuki Yamaguchi, Takashi Utsumi
-
Patent number: 6859079Abstract: An operation control signal for an oscillator producing an internal clock signal phase-locked with a basic clock signal is applied to a second internal clock generating circuit. In the second internal clock generating circuit, with reference to the applied operation control signal, a control signal adjusting a phase and/or frequency difference between a synchronization target signal and a second internal clock signal is produced to adjust a phase and/or frequency of the second internal clock signal. A plurality of internal clock signals different in phase and/or frequency can be generated accurately and stably.Type: GrantFiled: May 22, 2003Date of Patent: February 22, 2005Assignee: Renesas Technology Corp.Inventors: Yoshiyuki Haraguchi, Kiyoshi Adachi, Takashi Utsumi, Danichi Komatsu, Hiroyuki Kosaka
-
Publication number: 20040157576Abstract: A receiver of a communication device includes: a differential amplification circuit; two capacitors for applying only the amplitude components of two input clock signals complementary to each other to the gates of two N-channel MOS transistors of the differential amplification circuit; and an initialization circuit for applying a predetermined reference potential to the gates of the two N-channel MOS transistors in a non data communication state. Thus, it is possible to make a quick and stable transition from a non data communication state to a data communication state.Type: ApplicationFiled: November 19, 2003Publication date: August 12, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventors: Kiyoshi Adachi, Danichi Komatsu, Takashi Utsumi, Yoshiyuki Haraguchi, Hiroyuki Kousaka, Masahiro Yokoyama
-
Patent number: 6765818Abstract: Each memory cell of an SRAM has normally a pair of inverters cross-connected to each other, a pair of transistors connected to output ends of the inverters respectively, a word line connected to gates of the transistors, and a bit line and an inverted bit line connected to the transistors respectively. To produce a storage data fixing memory cell functioning as that of a ROM from one normal memory cell, an input end of one inverter is disconnected from the output end of the other inverter and is connected to a low electric potential terminal or is connected to a high electric potential terminal. Therefore, preset data can be stored in the storage data fixing memory cell without changing characteristics of the SRAM in the changing of the normal cell memory to the storage data fixing memory cell.Type: GrantFiled: March 10, 2003Date of Patent: July 20, 2004Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Teruaki Kanzaki, Takashi Utsumi
-
Publication number: 20040104753Abstract: An operation control signal for an oscillator producing an internal clock signal phase-locked with a basic clock signal is applied to a second internal clock generating circuit. In the second internal clock generating circuit, with reference to the applied operation control signal, a control signal adjusting a phase and/or frequency difference between a synchronization target signal and a second internal clock signal is produced to adjust a phase and/or frequency of the second internal clock signal. A plurality of internal clock signals different in phase and/or frequency can be generated accurately and stably.Type: ApplicationFiled: May 22, 2003Publication date: June 3, 2004Applicant: Renesas Technology Corp.Inventors: Yoshiyuki Haraguchi, Kiyoshi Adachi, Takashi Utsumi, Danichi Komatsu, Hiroyuki Kosaka
-
Publication number: 20040047178Abstract: Each memory cell of an SRAM has normally a pair of inverters cross-connected to each other, a pair of transistors connected to output ends of the inverters respectively, a word line connected to gates of the transistors, and a bit line and an inverted bit line connected to the transistors respectively. To produce a storage data fixing memory cell functioning as that of a ROM from one normal memory cell, an input end of one inverter is disconnected from the output end of the other inverter and is connected to a low electric potential terminal or is connected to a high electric potential terminal. Therefore, preset data can be stored in the storage data fixing memory cell without changing characteristics of the SRAM in the changing of the normal cell memory to the storage data fixing memory cell.Type: ApplicationFiled: March 10, 2003Publication date: March 11, 2004Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Teruaki Kanzaki, Takashi Utsumi
-
Patent number: 6493833Abstract: A microcomputer including a built-in storage portion capable of executing an evaluation program by an ICE through a simple operation also when the evaluation program cannot be written in the built-in ROM is obtained. A debugging circuit (2) outputs a reset vector selection signal (S2) indicating generation of a reset vector (V1/V2) in response to a control signal (S1) indicating a normal mode/a RAM starting mode, and a reset circuit (3) generates a reset vector (V1/V2) indicating a starting address (A1/A2) after reset cancellation by indication of the reset vector selection signal (S2). The microcomputer can be set to execute the evaluation program from the starting address (A2) on a RAM area (5) after reset cancellation by registering the evaluation program (start address=starting address (A2)) in the RAM area (5) from the ICE through the debugging circuit (2) and thereafter supplying a control signal (S1) indicating the RAM starting mode to the debugging circuit (2).Type: GrantFiled: November 15, 1999Date of Patent: December 10, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Takashi Utsumi
-
Patent number: 6482062Abstract: A method of forming barrier ribs for a plasma display panel comprising the steps of: forming an uncured barrier rib material layer on a glass substrates; rolling on said barrier rib material layer a roller having an intaglio recessed pattern corresponding to a desired pattern for the barrier ribs to be formed, so that the freestanding structures of the rib material corresponding to the barrier ribs; and drying and firing the barrier rib material shaped into the freestanding structures, whereby the barrier ribs for partitioning discharge cells are formed on the glass substrate. A phosphor can be filled in the discharge cells by rolling a roller having groove or recessed pattern corresponding the barrier rib pattern on the phosphor material laminated on the substrate. A phosphor material sheet used to form discharge cells on the substrate and manufacturing method thereof are also provided.Type: GrantFiled: February 18, 2000Date of Patent: November 19, 2002Assignee: Fuji Photo Film Co., Ltd.Inventors: Yasunori Yao, Akihiro Kanezawa, Nobuya Yamazaki, Takashi Utsumi, Tooru Kubo
-
Patent number: 6469946Abstract: A semiconductor memory includes a test memory cell block and a test memory cell selector. The test memory cell block includes a plurality of memory cells that store bit values opposite to each other in adjacent memory cells. The test memory cell selector varies the potential of precharged bit lines by asserting one of the word lines of the test memory cell block, and selects as a memory cell to be tested, a memory cell that is connected to a bit line between the bit lines that changes their potentials in the test memory cell block. It can solve a problem of a conventional semiconductor memory in that it is very difficult to test the function of a circuit installed for suppressing the interference between adjacent bit lines.Type: GrantFiled: June 13, 2001Date of Patent: October 22, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takashi Utsumi, Kiyoshi Adachi
-
Publication number: 20020054526Abstract: A semiconductor memory includes a test memory cell block and a test memory cell selector. The test memory cell block includes a plurality of memory cells that store bit values opposite to each other in adjacent memory cells. The test memory cell selector varies the potential of precharged bit lines by asserting one of the word lines of the test memory cell block, and selects as a memory cell to be tested, a memory cell that is connected to a bit line between the bit lines that changes their potentials in the test memory cell block. It can solve a problem of a conventional semiconductor memory in that it is very difficult to test the function of a circuit installed for suppressing the interference between adjacent bit lines.Type: ApplicationFiled: June 13, 2001Publication date: May 9, 2002Inventors: Takashi Utsumi, Kiyoshi Adachi
-
Publication number: 20010055167Abstract: A slave disk is held by a stage, and a holder holding a master disk is displaced to the side of the slave disk through use of a linear slider so that the master disk is in face-to-face contact with the slave disk. Then, vacuum suction is executed from a suction port for close contact of the stage to achieve close contact between the slave disk and the master disk. Under this close contact condition, a permanent magnet is rotated to transfer magnetic signals recorded on the master disk to the slave disk.Type: ApplicationFiled: April 20, 2001Publication date: December 27, 2001Inventors: Nobuhide Matsuda, Takashi Utsumi, Masaki Kondo
-
Patent number: 6012294Abstract: In a heat pump type air conditioner, a refrigerant ejection port of a compressor in a refrigerating cycle thereof is connected to a refrigerant inflow port of an outdoor heat exchanger via a bypass pipe with a shut-off valve, and temperature sensors detect the temperatures of the refrigerant inflow and runoff port sides of an outdoor heat exchanger. In a heating operation mode, when the temperature of the refrigerant inflow or runoff port side reaches a certain value or lower that requires defrosting, the shut-off valve of the bypass pipe is "opened" to start defrosting using the hot gas bypass defrosting method.Type: GrantFiled: December 14, 1998Date of Patent: January 11, 2000Assignee: Fujitsu General LimitedInventor: Takashi Utsumi
-
Patent number: 4163679Abstract: A chromium-free treatment for aluminum imparts corrosion resistance and paint receptivity to the surface. The process is sequential and includes a first contact with an aqueous alkaline solution (pH above 10) containing complexed iron ion, water rinsing, and then contact with an aqueous acidic organic tannin-containing composition.Type: GrantFiled: March 30, 1978Date of Patent: August 7, 1979Assignee: Oxy Metal Industries CorporationInventors: Yoshio Nagae, Takashi Utsumi