Patents by Inventor Takashi Yamaki
Takashi Yamaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130235668Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.Type: ApplicationFiled: April 20, 2013Publication date: September 12, 2013Applicants: HITACHI ULSI SYSTEMS CO., LTD., RENESAS ELECTRONICS CORPORATIONInventors: Toshihiro TANAKA, Yukiko UMEMOTO, Mitsuru HIRAKI, Yutaka SHINAGAWA, Masamichi FUJITO, Kazufumi SUZUKAWA, Hiroyuki TANIKAWA, Takashi YAMAKI, Yoshiaki KAMIGAKI, Shinichi MINAMI, Kozo KATAYAMA, Nozomu MATSUZAKI
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Patent number: 8426904Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.Type: GrantFiled: September 1, 2011Date of Patent: April 23, 2013Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Toshihiro Tanaka, Yukiko Umemoto, Mitsuru Hiraki, Yutaka Shinagawa, Masamichi Fujito, Kazufumi Suzukawa, Hiroyuki Tanikawa, Takashi Yamaki, Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Nozomu Matsuzaki
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Patent number: 8385134Abstract: When a leakage type determining circuit determines that leakage current components of a gate leakage and a substrate leakage are larger in a resume standby mode, a VDDR regulator generates a power supply voltage VDDR at a first voltage level lower than a power supply voltage VDD, and supplies the voltage as a power supply voltage VDDR1 to an SRAM module via a selector switch. When the leakage type determining circuit determines that a leakage current of a channel leakage is larger, the VDDR regulator supplies the power supply voltage VDDR1 higher than the first voltage level and lower than the power supply voltage VDD to the SRAM module. Also, an ARVSS regulator supplies a cell source power supply voltage higher than a reference voltage to an SRAM module in another region.Type: GrantFiled: September 24, 2011Date of Patent: February 26, 2013Assignee: Renesas Electronics CorporationInventor: Takashi Yamaki
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Publication number: 20130021832Abstract: In a semiconductor device, memory modules each having a low power consumption mode that is enabled and disabled by a control signal belong to a memory block. A transmission path of the control signal is provided such that the control signal is inputted in parallel to the memory module via an inside-of-module path, and such that the control signal is outputted by a particular memory module of the memory modules via the inside-of-module path to a downstream outside-of-module path. The particular memory module in the memory block is selected such that it has a greater storage capacity than the other memory modules belonging to this same memory block have.Type: ApplicationFiled: June 25, 2012Publication date: January 24, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Takashi YAMAKI
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Publication number: 20120081975Abstract: When a leakage type determining circuit determines that leakage current components of a gate leakage and a substrate leakage are larger in a resume standby mode, a VDDR regulator generates a power supply voltage VDDR at a first voltage level lower than a power supply voltage VDD, and supplies the voltage as a power supply voltage VDDR1 to an SRAM module via a selector switch. When the leakage type determining circuit determines that a leakage current of a channel leakage is larger, the VDDR regulator supplies the power supply voltage VDDR1 higher than the first voltage level and lower than the power supply voltage VDD to the SRAM module. Also, an ARVSS regulator supplies a cell source power supply voltage higher than a reference voltage to an SRAM module in another region.Type: ApplicationFiled: September 24, 2011Publication date: April 5, 2012Inventor: Takashi YAMAKI
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Patent number: 8017986Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.Type: GrantFiled: March 5, 2010Date of Patent: September 13, 2011Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Toshihiro Tanaka, Yukiko Umemoto, Mitsuru Hiraki, Yutaka Shinagawa, Masamichi Fujito, Kazufumi Suzukawa, Hiroyuki Tanikawa, Takashi Yamaki, Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Nozomu Matsuzaki
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Publication number: 20110080779Abstract: A phase change memory includes a memory cell with a phase change element storing data according to level change of a resistance value in association with phase change, a write circuit converting the phase change element to an amorphous state or a polycrystalline state according to the logic of write data in a write operation mode, a read circuit reading out stored data from the phase change element in a readout operation mode, and a discharge circuit applying a discharge voltage to the phase change element to remove electrons trapped in the phase change element in a discharge operation mode. Accordingly, variation in the resistance value at the phase change element can be suppressed.Type: ApplicationFiled: December 15, 2010Publication date: April 7, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Fumihiko NITTA, Yoshikazu IIDA, Takashi YAMAKI
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Patent number: 7881102Abstract: A phase change memory includes a memory cell with a phase change element storing data according to level change of a resistance value in association with phase change, a write circuit converting the phase change element to an amorphous state or a polycrystalline state according to the logic of write data in a write operation mode, a read circuit reading out stored data from the phase change element in a readout operation mode, and a discharge circuit applying a discharge voltage to the phase change element to remove electrons trapped in the phase change element in a discharge operation mode. Accordingly, variation in the resistance value at the phase change element can be suppressed.Type: GrantFiled: February 12, 2009Date of Patent: February 1, 2011Assignee: Renesas Electronics CorporationInventors: Fumihiko Nitta, Yoshikazu Iida, Takashi Yamaki
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Publication number: 20100157689Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.Type: ApplicationFiled: March 5, 2010Publication date: June 24, 2010Inventors: TOSHIHIRO TANAKA, Yukiko Umemoto, Mitsuru Hiraki, Yutaka Shinagawa, Masamichi Fujito, Kazufumi Suzukawa, Hiroyuki Tanikawa, Takashi Yamaki, Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Nozomu Matsuzaki
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Patent number: 7700992Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.Type: GrantFiled: June 19, 2008Date of Patent: April 20, 2010Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Toshihiro Tanaka, Yukiko Umemoto, Mitsuru Hiraki, Yutaka Shinagawa, Masamichi Fujito, Kazufumi Suzukawa, Hiroyuki Tanikawa, Takashi Yamaki, Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Nozomu Matsuzaki
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Publication number: 20090207652Abstract: A phase change memory includes a memory cell with a phase change element storing data according to level change of a resistance value in association with phase change, a write circuit converting the phase change element to an amorphous state or a polycrystalline state according to the logic of write data in a write operation mode, a read circuit reading out stored data from the phase change element in a readout operation mode, and a discharge circuit applying a discharge voltage to the phase change element to remove electrons trapped in the phase change element in a discharge operation mode. Accordingly, variation in the resistance value at the phase change element can be suppressed.Type: ApplicationFiled: February 12, 2009Publication date: August 20, 2009Inventors: Fumihiko Nitta, Yoshikazu Iida, Takashi Yamaki
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Patent number: 7551493Abstract: A data processing device which selects either emission of electrons from a nonvolatile memory cell or injection of electrons into it for each bit. A memory array includes a plurality of nonvolatile memory cells each having a pair of a first MOS transistor and a second MOS transistor where the first transistor has a charge retention layer and a memory gate and is used for data storage and the second transistor has a control gate and selectively connects the first transistor to a bit line. When negative voltage is applied to a memory gate, electrons held by a charge retention layer are emitted through hot carriers generated in a nonvolatile memory cell channel region for erasing; and when positive voltage is applied to the memory gate, electrons are injected into the charge retention layer through hot carriers generated in the nonvolatile memory cell channel region for writing and controls the generation and suppression of hot carriers by means of bit line voltage on each bit line.Type: GrantFiled: June 21, 2007Date of Patent: June 23, 2009Assignee: Renesas Technology Corp.Inventors: Akira Kato, Toshihiro Tanaka, Takashi Yamaki
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Patent number: 7529126Abstract: Disclosed here is a method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a memory cell, a voltage of about 8V is applied to the memory gate line, a voltage of about 5V is applied to the source line, a voltage of about 1.5V is applied to the selected gate line respectively. At that time, in the writing circuit, the writing pulse is 0, the writing latch output a High signal, and a NAND-circuit outputs a Low signal. And, a constant current of about 1iA flows in a constant current source transistor and the bit line is discharged by a constant current of about 1iA to flow a current in the memory cell.Type: GrantFiled: June 23, 2006Date of Patent: May 5, 2009Assignee: Renesas Technology Corp.Inventors: Toshihiro Tanaka, Takashi Yamaki, Yutaka Shinagawa, Daisuke Okada, Digh Hisamoto, Kan Yasui, Tetsuya Ishimaru
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Publication number: 20090010072Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.Type: ApplicationFiled: June 19, 2008Publication date: January 8, 2009Inventors: Toshihiro TANAKA, Yukiko Umemoto, Mitsuru Hiraki, Yutaka Shinagawa, Masamichi Fujito, Kazufumi Suzukawa, Hiroyuki Tanikawa, Takashi Yamaki, Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Nozomu Matsuzaki
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Patent number: 7414283Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.Type: GrantFiled: May 2, 2006Date of Patent: August 19, 2008Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Toshihiro Tanaka, Yukiko Umemoto, Mitsuru Hiraki, Yutaka Shinagawa, Masamichi Fujito, Kazufumi Suzukawa, Hiroyuki Tanikawa, Takashi Yamaki, Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Nozomu Matsuzaki
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Patent number: 7376015Abstract: Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.Type: GrantFiled: August 5, 2005Date of Patent: May 20, 2008Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Kazufumi Suzukawa, Masamichi Fujito, Takashi Yamaki, Kiichi Makuta, Masashi Wada, Yoshiki Kawajiri
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Patent number: 7339827Abstract: In connection with rise and fall of a word line bias, the present invention adopts a procedure such that a diffusion region voltage Vs on a memory transistor side is changed, and after the voltage Vs passes a certain intermediate value Vsx, a gate voltage Vmg of the memory transistor is changed. Alternatively, there is adopted a procedure such that the gate voltage Vmg of the memory transistor is changed, and after the voltage Vmg passes a certain intermediate value Vmgx, the diffusion layer voltage Vs on the memory transistor side is changed. The values of Vsx and Vmgx are determined from the magnitude of the electric field in a gate insulating film not causing FN tunneling electron injection that causes a change in threshold voltage and the magnitude of a potential barrier against holes not causing BTBT hot hole injection.Type: GrantFiled: June 8, 2005Date of Patent: March 4, 2008Assignee: Renesas Technology Corp.Inventors: Kan Yasui, Digh Hisamoto, Toshihiro Tanaka, Takashi Yamaki
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Publication number: 20070285984Abstract: A data processing device which selects either emission of electrons from a nonvolatile memory cell or injection of electrons into it for each bit. A memory array includes a plurality of nonvolatile memory cells each having a pair of a first MOS transistor and a second MOS transistor where the first transistor has a charge retention layer and a memory gate and is used for data storage and the second transistor has a control gate and selectively connects the first transistor to a bit line. When negative voltage is applied to a memory gate, electrons held by a charge retention layer are emitted through hot carriers generated in a nonvolatile memory cell channel region for erasing; and when positive voltage is applied to the memory gate, electrons are injected into the charge retention layer through hot carriers generated in the nonvolatile memory cell channel region for writing and controls the generation and suppression of hot carriers by means of bit line voltage on each bit line.Type: ApplicationFiled: June 21, 2007Publication date: December 13, 2007Inventors: Akira KATO, Toshihiro Tanaka, Takashi Yamaki
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Patent number: 7286410Abstract: A semiconductor integrated circuit has a first nonvolatile memory area and a second nonvolatile memory area to store information in accordance with a variable threshold voltage. At least one condition of the following conditions of the first nonvolatile memory area is made different from that of the second nonvolatile memory area: erase verify determination memory gate voltage, erase verify determination memory current, write verify determination memory gate voltage, write verify determination memory current, erase voltage, erase voltage application time, write voltage, and write voltage application time in the first nonvolatile memory area.Type: GrantFiled: August 3, 2005Date of Patent: October 23, 2007Assignee: Renesas Technology Corp.Inventors: Hiroyuki Tanikawa, Toshihiro Tanaka, Yutaka Shinagawa, Takashi Yamaki
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Patent number: 7248504Abstract: A data processing device which selects either emission of electrons from a nonvolatile memory cell or injection of electrons into it for each bit. A memory array includes a plurality of nonvolatile memory cells each having a pair of a first MOS transistor and a second MOS transistor where the first transistor has a charge retention layer and a memory gate and is used for data storage and the second transistor has a control gate and selectively connects the first transistor to a bit line. When negative voltage is applied to a memory gate, electrons held by a charge retention layer are emitted through hot carriers generated in a nonvolatile memory cell channel region for erasing; and when positive voltage is applied to the memory gate, electrons are injected into the charge retention layer through hot carriers generated in the nonvolatile memory cell channel region for writing and controls the generation and suppression of hot carriers by means of bit line voltage on each bit line.Type: GrantFiled: June 1, 2005Date of Patent: July 24, 2007Assignee: Renesas Technology Corp.Inventors: Akira Kato, Toshihiro Tanaka, Takashi Yamaki