Patents by Inventor Takashi Yunogami
Takashi Yunogami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7737023Abstract: In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes an organosiloxane as a main component, the recess, such as a trench or hole, is formed by subjecting the organic insulating film to plasma dry etching in a CF-based gas/N2/Ar gas in order to suppress the formation of an abnormal shape on the bottom of the recess, upon formation of a photoresist film over the organic insulating film, followed by formation of the recess therein with the photoresist film as an etching mask.Type: GrantFiled: August 19, 2008Date of Patent: June 15, 2010Assignee: Renesas Technology CorporationInventors: Shouochi Uno, Atsushi Maekawa, Takashi Yunogami, Kazutami Tago, Kazuo Nojiri, Shuntaro Machida, Takafumi Tokunaga
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Publication number: 20090011592Abstract: In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes an organosiloxane as a main component, the recess, such as a trench or hole, is formed by subjecting the organic insulating film to plasma dry etching in a CF-based gas/N2/Ar gas in order to suppress the formation of an abnormal shape on the bottom of the recess, upon formation of a photoresist film over the organic insulating film, followed by formation of the recess therein with the photoresist film as an etching mask.Type: ApplicationFiled: August 19, 2008Publication date: January 8, 2009Inventors: Shouichi Uno, Atsushi Maekawa, Takashi Yunogami, Kazutami Tago, Kazuo Nojiri, Shuntaro Machida, Takafumi Tokunaga
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Patent number: 7419902Abstract: In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes an organosiloxane as a main component, the recess, such as a trench or hole, is formed by subjecting the organic insulating film to plasma dry etching in a CF-based gas/N2/Ar gas in order to suppress the formation of an abnormal shape on the bottom of the recess, upon formation of a photoresist film over the organic insulating film, followed by formation of the recess therein with the photoresist film as an etching mask.Type: GrantFiled: April 13, 2005Date of Patent: September 2, 2008Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., LtdInventors: Shouochi Uno, Atsushi Maekawa, Takashi Yunogami, Kazutami Tago, Kazuo Nojiri, Shuntaro Machida, Takafumi Tokunaga
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Patent number: 7264677Abstract: Ruthenium, osmium and their oxides can be etched simply and rapidly by supplying an atomic oxygen-donating gas, typically ozone, to the aforementioned metals and their oxides through catalysis between the metals and their oxides, and the ozone without any damages to wafers and reactors and application of the catalysis not only to the etching but also to chamber cleaning ensures stable operation of reactors and production of high quality devices.Type: GrantFiled: October 19, 2005Date of Patent: September 4, 2007Assignee: Renesas Technology Corp.Inventors: Miwako Nakahara, Toshiyuki Arai, Shigeru Ohno, Takashi Yunogami, Sukeyoshi Tsunekawa, Kazuto Watanabe
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Patent number: 7025896Abstract: Ruthenium, osmium and their oxides can be etched simply and rapidly by supplying an atomic oxygen-donating gas, typically ozone, to the aforementioned metals and their oxides through catalysis between the metals and their oxides, and the ozone without any damages to wafers and reactors and application of the catalysis not only to the etching but also to chamber cleaning ensures stable operation of reactors and production of high quality devices.Type: GrantFiled: June 13, 2003Date of Patent: April 11, 2006Assignee: Renesas Technology Corp.Inventors: Miwako Nakahara, Toshiyuki Arai, Shigeru Ohno, Takashi Yunogami, Sukeyoshi Tsunekawa, Kazuto Watanabe
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Publication number: 20060037627Abstract: Ruthenium, osmium and their oxides can be etched simply and rapidly by supplying an atomic oxygen-donating gas, typically ozone, to the aforementioned metals and their oxides through catalysis between the metals and their oxides, and the ozone without any damages to wafers and reactors and application of the catalysis not only to the etching but also to chamber cleaning ensures stable operation of reactors and production of high quality devices.Type: ApplicationFiled: October 19, 2005Publication date: February 23, 2006Inventors: Miwako Nakahara, Toshiyuki Arai, Shigeru Ohno, Takashi Yunogami, Sukeyoshi Tsunekawa, Kazuto Watanabe
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Patent number: 6998325Abstract: An insulating-film composition containing an insulating-film precursor and a pore-generating material is applied onto a surface of a semiconductor substrate, and a first heat treatment is performed to polymerize the insulating-film precursor without vaporizing the pore-generating material, to form a non-porous insulating film. Next, a resist pattern is formed on the non-porous insulating film, and dry etching is performed, using the resist pattern as a mask, to form a trench in the non-porous insulating film. After removing the resist pattern by ashing, the surface of the semiconductor substrate is cleaned. Next, a second heat treatment is performed to remove the pore-generating material from the non-porous insulating film and to form a porous insulating film. Thereafter, a copper layer is deposited in the trench on a barrier-metal film to form copper wiring.Type: GrantFiled: November 4, 2004Date of Patent: February 14, 2006Assignee: Renesas Technology Corp.Inventors: Takashi Yunogami, Kaori Misawa
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Publication number: 20050186801Abstract: In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes an organosiloxane as a main component, the recess, such as a trench or hole, is formed by subjecting the organic insulating film to plasma dry etching in a CF-based gas/N2/Ar gas in order to suppress the formation of an abnormal shape on the bottom of the recess, upon formation of a photoresist film over the organic insulating film, followed by formation of the recess therein with the photoresist film as an etching mask.Type: ApplicationFiled: April 13, 2005Publication date: August 25, 2005Inventors: Shouochi Uno, Atsushi Maekawa, Takashi Yunogami, Kazutami Tago, Kazuo Nojiri, Shuntaro Machida, Takafumi Tokunaga
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Publication number: 20050101157Abstract: An insulating-film composition containing an insulating-film precursor and a pore-generating material is applied onto a surface of a semiconductor substrate, and a first heat treatment is performed to polymerize the insulating-film precursor without vaporizing the pore-generating material, to form a non-porous insulating film. Next, a resist pattern is formed on the non-porous insulating film, and dry etching is performed, using the resist pattern as a mask, to form a trench in the non-porous insulating film. After removing the resist pattern by ashing, the surface of the semiconductor substrate is cleaned. Next, a second heat treatment is performed to remove the pore-generating material from the non-porous insulating film and to form a porous insulating film. Thereafter, a copper layer is deposited in the trench on a barrier-metal film to form copper wiring.Type: ApplicationFiled: November 4, 2004Publication date: May 12, 2005Applicant: Semiconductor Leading Edge Technologies, Inc.Inventors: Takashi Yunogami, Kaori Misawa
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Patent number: 6774020Abstract: Insulating films 34 through 38 (of which insulating films 34, 36, 38 are silicon nitride films and insulating films 35, 38 are silicon oxide films) are sequentially formed on the wires 33 of the fourth wiring layer and groove pattern 40 is transferred into the insulating film 38 by means of photolithography. An anti-reflection film 41 is formed to fill the grooves 40 of the insulating film 38 and then a resist film 42 carrying a hole pattern 43 is formed. The films are subjected to an etching operation in the presence of the resist film 42 to transfer the hole pattern into the insulating films 38, 37, 36 and part of the insulating film 35. Subsequently, the resist film 42 and the anti-reflection film 41 are removed and the groove pattern 40 and the hole pattern 43 are transferred respectively into the insulating film 37 and the insulating film 35 by using the insulating film 38 as mask.Type: GrantFiled: January 31, 2003Date of Patent: August 10, 2004Assignee: Renesas Technology Corp.Inventors: Shinichi Fukada, Kazuo Nojiri, Takashi Yunogami, Shoji Hotta, Hideo Aoki, Takayuki Oshima, Nobuyoshi Kobayashi
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Patent number: 6756262Abstract: Conduction reliability between a capacitor upper electrode and a plug connected to an upper layer wire is kept high to prevent connection defects and to reduce the resistance of the capacitor upper electrode. In a capacitor of a DRAM comprising a lower electrode 45 made of ruthenium, a capacitor insulating film 50 made of BST and an upper electrode 49, the upper electrode 49 has a laminate structure comprising a ruthenium film 47 formed on the side of the capacitor insulating film 50 and a tungsten film 48 formed over the former.Type: GrantFiled: November 9, 2000Date of Patent: June 29, 2004Assignee: Hitachi, Ltd.Inventors: Yoshitaka Nakamura, Isamu Asano, Satoru Yamada, Tsugio Takahashi, Yuzuru Ohji, Masayoshi Hirasawa, Takashi Yunogami, Tomonori Sekiguchi
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Publication number: 20030205553Abstract: Ruthenium, osmium and their oxides can be etched simply and rapidly by supplying an atomic oxygen-donating gas, typically ozone, to the aforementioned metals and their oxides through catalysis between the metals and their oxides, and the ozone without any damages to wafers and reactors and application of the catalysis not only to the etching but also to chamber cleaning ensures stable operation of reactors and production of high quality devices.Type: ApplicationFiled: June 13, 2003Publication date: November 6, 2003Inventors: Miwako Nakahara, Toshiyuki Arai, Shigeru Ohno, Takashi Yunogami, Sukeyoshi Tsunekawa, Kazuto Watanabe
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Patent number: 6613242Abstract: Ruthenium, osmium and their oxides can be etched simply and rapidly by supplying an atomic oxygen-donating gas, typically ozone, to the aforementioned metals and their oxides through catalysis between the metals and their reactors and application of the catalysis not only to the etching but also to chamber cleaning ensures stable operation of reactors and production of high quality devices.Type: GrantFiled: October 23, 2001Date of Patent: September 2, 2003Inventors: Miwako Nakahara, Toshiyuki Arai, Shigeru Ohno, Takashi Yunogami, Sukeyoshi Tsunekawa, Kazuto Watanabe
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Patent number: 6607988Abstract: With a view to providing a technique for highly-selective etching of Ru (ruthenium) using a photoresist as an etching mask, an Ru-film, which is an lower electrode material deposited on the side walls and bottom surface of a hole, is covered with a photoresist film, followed by isotropic dry etching in a gas atmosphere containing an ozone gas, whereby a portion of the Ru film outside of the hole is removed.Type: GrantFiled: December 28, 2000Date of Patent: August 19, 2003Assignee: Hitachi, Ltd.Inventors: Takashi Yunogami, Yoshitaka Nakamura, Kazuo Nojiri, Sukeyoshi Tsunekawa, Toshiyuki Arai, Miwako Nakahara, Shigeru Ohno, Tomonori Saeki, Masaru Izawa
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Publication number: 20030139031Abstract: Insulating films 34 through 38 (of which insulating films 34, 36, 38 are silicon nitride films and insulating films 35, 38 are silicon oxide films) are sequentially formed on the wires 33 of the fourth wiring layer and groove pattern 40 is transferred into the insulating film 38 by means of photolithography. An anti-reflection film 41 is formed to fill the grooves 40 of the insulating film 38 and then a resist film 42 carrying a hole pattern 43 is formed. The films are subjected to an etching operation in the presence of the resist film 42 to transfer the hole pattern into the insulating films 38, 37, 36 and part of the insulating film 35. Subsequently, the resist film 42 and the anti-reflection film 41 are removed and the groove pattern 40 and the hole pattern 43 are transferred respectively into the insulating film 37 and the insulating film 35 by using the insulating film 38 as mask.Type: ApplicationFiled: January 31, 2003Publication date: July 24, 2003Inventors: Shinichi Fukada, Kazuo Nojiri, Takashi Yunogami, Shoji Hotta, Hideo Aoki, Takayuki Oshima, Nobuyoshi Kobayashi
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Patent number: 6555464Abstract: Insulating films 34 through 38 (of which insulating films 34, 36, 38 are silicon nitride films and insulating films 35, 38 are silicon oxide films) are sequentially formed on the wires 33 of the fourth wiring layer and groove pattern 40 is transferred into the insulating film 38 by means of photolithography. An anti-reflection film 41 is formed to fill the grooves 40 of the insulating film 38 and then a resist film 42 carrying a hole pattern 43 is formed. The films are subjected to an etching operation in the presence of the resist film 42 to transfer the hole pattern into the insulating films 38, 37, 36 and part of the insulating film 35. Subsequently, the resist film 42 and the anti-reflection film 41 are removed and the groove pattern 40 and the hole pattern 43 are transferred respectively into the insulating film 37 and the insulating film 35 by using the insulating film 38 as mask.Type: GrantFiled: January 17, 2002Date of Patent: April 29, 2003Assignee: Hitachi, Ltd.Inventors: Shinichi Fukada, Kazuo Nojiri, Takashi Yunogami, Shoji Hotta, Hideo Aoki, Takayuki Oshima, Nobuyoshi Kobayashi
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Patent number: 6537461Abstract: Ruthenium, osmium and their oxides can be etched simply and rapidly by supplying an atomic oxygen-donating gas, typically ozone, to the aforementioned metals and their oxides through catalysis between the metals and their oxides, and the ozone without any damages to wafers and reactors and application of the catalysis not only to the etching but also to chamber cleaning ensures stable operation of reactors and production of high quality devices.Type: GrantFiled: April 24, 2000Date of Patent: March 25, 2003Assignee: Hitachi, Ltd.Inventors: Miwako Nakahara, Toshiyuki Arai, Shigeru Ohno, Takashi Yunogami, Sukeyoshi Tsunekawa, Kazuto Watanabe
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Patent number: 6528400Abstract: Insulating films 34 through 38 (of which insulating films 34, 36, 38 are silicon nitride films and insulating films 35, 38 are silicon oxide films) are sequentially formed on the wires 33 of the fourth wiring layer and groove pattern 40 is transferred into the insulating film 38 by means of photolithography. An anti-reflection film 41 is formed to fill the grooves 40 of the insulating film 38 and then a resist film 42 carrying a hole pattern 43 is formed. The films are subjected to an etching operation in the presence of the resist film 42 to transfer the hole pattern into the insulating films 38, 37, 36 and part of the insulating film 35. Subsequently, the resist film 42 and the anti-reflection film 41 are removed and the groove pattern 40 and the hole pattern 43 are transferred respectively into the insulating film 37 and the insulating film 35 by using the insulating film 38 as mask.Type: GrantFiled: December 3, 2001Date of Patent: March 4, 2003Assignee: Hitachi, Ltd.Inventors: Shinichi Fukada, Kazuo Nojiri, Takashi Yunogami, Shoji Hotta, Hideo Aoki, Takayuki Oshima, Nobuyoshi Kobayashi
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Patent number: 6506674Abstract: A hole is formed on an insulating film made of silicon oxide by selectively plasma-etching the insulating film with an etching gas containing C5F8, O2, and Ar firstly under a condition in which the deposition property of a polymer layer is weak and secondly under a condition in which that of the polymer layer is strong.Type: GrantFiled: September 28, 2001Date of Patent: January 14, 2003Assignees: Hitachi, Ltd., NEC CorporationInventors: Takenobu Ikeda, Masahiro Tadokoro, Masaru Izawa, Takashi Yunogami
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Patent number: 6497992Abstract: In order that reaction products of low vapor pressure may be prevented from being deposited on the side wall of a predetermined pattern when this pattern is to be formed by dry-etching a Pt film or a PZT film, a resist mask 54 having a rounded outer periphery at its head is used when the Pt film 53 deposited on a semiconductor substrate 50 is to be dry-etched. After this dry-etching, moreover, an overetching of a proper extent is performed to completely remove the side wall deposited film 55 which is left on the side of the pattern. The resist mask 54 is formed by exposing and developing a benzophenone novolak resist and subsequently by heating to set it while irradiating it, if necessary, with ultraviolet rays.Type: GrantFiled: April 17, 2000Date of Patent: December 24, 2002Assignee: Hitachi, Ltd.Inventors: Takashi Yunogami, Shunji Sasabe, Kazuyuki Suko, Jun Abe, Takao Kumihashi, Fumio Murai