Patents by Inventor Takashige Baba

Takashige Baba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7469351
    Abstract: An object of the present invention is to provide a management technique for managing power supply modules. In multiple computer equipment 100, in response to a load state, if an operation system 1101 issues a command that changes a processor state of a processor 1021 to a sleep state, a management module 107 is notified through a management network MI that the processor state has changed. The management module 107 holds a system information 108, and performs the steps of: updating system information 108 because the processor state has changed; from this system information 108, calculating the power consumption required for the multiple computer equipment 100; determining the number of required AC-DC power supply modules 1061, 1062, . . . to be operated; and changing the number of operating AC-DC power supply modules 1061, 1062, . . . by use of a control interface PA.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: December 23, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Takashige Baba, Kazuhide Horimoto
  • Publication number: 20080256266
    Abstract: To improve throughput in data transfer in a remote I/O system, this invention provides a computer system including: a host computer; a device which communicates with the host computer; and a network which connects the host computer and the device, in which the device is coupled to the network via a device bridge including a bridge memory, and the host computer includes a host memory and a device driver. The device driver writes, when at least one of data and an address is written in the host memory, in the bridge memory the at least one of the data and address stored through the writing in the host memory; and sends a data transfer request to the device bridge, and the device bridge reads, upon reception of the data transfer request, an address from a predetermined area; and reads data from an area that is indicated by the read address.
    Type: Application
    Filed: September 5, 2007
    Publication date: October 16, 2008
    Inventors: Jun Okitsu, Yoshiko Yasuda, Takashige Baba
  • Patent number: 7418587
    Abstract: A compound computer machine in which a plurality of modules are installed in one casing and in which trouble of management in combining modules to construct a computer machine is reduced. In the compound computer machine including a processor module; a component module which is combined with the processor module to construct a computer machine; and a management module which manages the processor module and the component module, the management module has module combination constraint information and priority information for constructing the computer machine, prepares installation information of the compound computer machine on receiving a request for constructing the computer machine, thereafter prepares module combination candidate information from the constraint information, and adds priority to the combination candidate information in a case where there exists the priority information to manage the constructions of the modules.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: August 26, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhide Horimoto, Takashige Baba
  • Patent number: 7389367
    Abstract: A method is provided for efficiently managing the connection of processor modules and input/output interface modules at a drastically reduced cost. A management server searches IFT and ST tables after receiving an instruction from the system management server to connect an input/output interface module to a processor, creates a condition list requested by the input/output interface module, and selects an input/output interface matching the condition list JL from an unassigned input/output interface module management table UNT. The management server next instructs the input/output interface switch to connect the processor with the selected input/output interface. The management server instructs the input/output device management server and the network management server to setup a connection utilizing the selected input/output interface, and rewrites the tables UNT and SPT.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: June 17, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Takashige Baba, Toshiaki Tarui, Yoshifumi Takamoto
  • Publication number: 20080140877
    Abstract: An IO adapter for guaranteeing the data transfer bandwidth on each capsule interface when multiple capsule interfaces jointly share the DMA engine of the IO adapter. An IO driver containing a capsule interface information table including bandwidth information and for setting the forming status of a pair of capsule interfaces and, during data transfer subdivides the descriptors for the capsule interfaces into multiple groups for each data buffer size satisfying the preset bandwidth information and, copies one group at each fixed sample time set by the descriptor registration means, into the descriptor ring and performs DMA transfer. To control this copy information, the IO driver contains a ring scheduler information table for managing the number of descriptor entries for the capsule interface cycle time and, a ring scheduler cancel means for renewing the entries in the ring scheduler information table each time one transmission of the descriptor group ends.
    Type: Application
    Filed: July 31, 2007
    Publication date: June 12, 2008
    Inventors: Takashige BABA, Yoshiko YASUDA, Jun OKITSU
  • Patent number: 7334164
    Abstract: In a storage device including plural disk controllers, the invention reduces time required for failure recovery when a failure occurs in the disk controllers. The storage device includes n (n>2, where n is an integer) disk controllers. The disk controller includes a cache memory. Data of the cache memory is copied to another cache memory. When a failure occurs in the disk controller, data not written to a disk of the data copied to the cache memory is transferred to further another cache memory.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: February 19, 2008
    Assignee: Hitachi, Ltd.
    Inventor: Takashige Baba
  • Publication number: 20070277046
    Abstract: To provide a power management method for an information platform, including: holding system configuration information indicating a correspondence between a logical system and a processing module constituting the logical system; holding power management information indicating a correspondence between information with which a type of the logical system can be specified, an operating condition of the logical system, and first power consumption for operating the logical system; selecting, the processing module which constitutes the logical system specified by a configuration request by referring to the system configuration information when receiving the configuration request of the logical system; calculating the first power consumption for operating the logical system based on the type and the operating condition included in the configuration request, and the power management information; and determining second power consumption to be supplied to the processing module based on the calculated first power consumpt
    Type: Application
    Filed: May 25, 2007
    Publication date: November 29, 2007
    Inventors: Yoshiko Yasuda, Takashige Baba, Jun Okitsu, Toshiaki Tarui
  • Patent number: 7277643
    Abstract: A signal communication apparatus of a clock reproduction system in which clock signals are extracted from each of parallel data signals for redigitizing each of the data signals. The apparatus includes a reference clock signal generating circuit which is comprised of a clock extraction circuit for extracting a clock signal from each of a plurality of bits of received data signals, and a clock signal selection circuit for selecting one of the extracted clock signals. Alternatively, the reference clock signal generating circuit may be comprised of a data signal selection circuit for selecting one of a plurality of received data signals, and a clock extraction circuit for extracting a clock signal from the selected bit. Based on the resultant reference clock signal, clock signals are obtained that are phase-adjusted for redigitizing each bit of the received data signals.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: October 2, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Takashige Baba, Tatsuya Saito, Masayoshi Yagyu, Shigeo Oomae
  • Publication number: 20070177522
    Abstract: There is a need for applying an appropriate QoS setting to a complex information platform apparatus capable of flexibly changing an apparatus configuration so as to ensure an intra-apparatus communication band and realize management communication independence. Multiple processing modules are combined to construct one or more processing units with different apparatus types. An apparatus template management table prepares multiple levels of setting specifications with different ensured bands for intra-apparatus communication corresponding to each apparatus type. One set of setting specification is selected from multiple levels of setting specifications prepared for an apparatus type settled at the time of configuration setting. A QoS setting management table is generated based on the selected setting specification. When the configuration is set or changed, setting verification means verifies whether or not a total of ensured bands associated with each adapter is within an allowable range.
    Type: Application
    Filed: January 22, 2007
    Publication date: August 2, 2007
    Inventors: Jun Okitsu, Yoshiko Yasuda, Takashige Baba, Toshiaki Tarui
  • Publication number: 20070168597
    Abstract: Module combination candidates which compose an information platform, to reduce human error when a platform is composed, and to permit automatic configuration changes. There is therefore provided a compound information platform comprising information platforms combining one or more universal processing modules and dedicated processing modules, wherein a management module has a means which computes processing module combination candidates when newly composing the information platform, computes the sum total value of the maximum guaranteed communication bandwidth of an IO protocol interface for each physical interconnection PL using an interface setting management information, adding an additional maximum guaranteed communication bandwidth due to a processing module combination candidate, and determining whether this is a possible module combination candidate by comparing the addition result with the maximum permitted communication bandwidth of each physical interconnection.
    Type: Application
    Filed: January 5, 2007
    Publication date: July 19, 2007
    Inventors: Takashige Baba, Yoshiko Yasuda, Jun Okitsu, Toshiaki Tarui
  • Publication number: 20070165659
    Abstract: An information platform system, the configuration thereof is able to change flexibly to meet the needs of the customers, and able to use a single adapter for multiple uses, wherein multiple general-purpose processing modules and dedicated processing modules for processing disks and external networks are connected to one another with switching hubs via respective adapters, and the platform system includes a management module having a system identifier management table specifying system type of the general-purpose processing modules, a functional set management table managing a functional set to be included by the general-purpose processing module of each system identifier, and the configuration management table managing the combination of the general-purpose processing modules and dedicated processing modules, and the management module selects a functional set from multiple functional sets, installs the selected functional set into a general-purpose processing module and an adapter, and manages the system conf
    Type: Application
    Filed: January 5, 2007
    Publication date: July 19, 2007
    Inventors: Yoshiko Yasuda, Takashige Baba, Jun Okitsu, Toshiaki Tarui
  • Patent number: 7216269
    Abstract: A signal transmit-receive device of the invention reduces the number of high-speed signal lines required for connecting a transmitting circuit group and a receiving circuit group, and for running a loopback test on a signal transmit-receive device. The loopback test circuit uses an error detecting circuit, a test signal producing circuit, and a wiring for transmitting error information. The error detecting circuit compares a test signal pattern defined in advance by a first communication device and a received signal pattern. The test signal producing circuit produces the test signal pattern based on error information. If an error is detected, the error signal is transmitted to the test signal producing circuit through the wiring. The test signal producing circuit produces a predetermined test signal pattern if the error signal DE has an L level; upon receiving H level, it sends back the predetermined test signal pattern to the first communication device.
    Type: Grant
    Filed: December 5, 2002
    Date of Patent: May 8, 2007
    Assignee: Renesas Technology Corporation
    Inventors: Takashige Baba, Tatsuya Saito, Hiroki Yamashita, Yusuke Takeuchi, Satoru Isomura
  • Publication number: 20060242438
    Abstract: An object of the present invention is to provide a management technique for managing power supply modules. In multiple computer equipment 100, in response to a load state, if an operation system 1101 issues a command that changes a processor state of a processor 1021 to a sleep state, a management module 107 is notified through a management network MI that the processor state has changed. The management module 107 holds a system information 108, and performs the steps of: updating system information 108 because the processor state has changed; from this system information 108, calculating the power consumption required for the multiple computer equipment 100; determining the number of required AC-DC power supply modules 1061, 1062, . . . to be operated; and changing the number of operating AC-DC power supply modules 1061, 1062, . . . by use of a control interface PA.
    Type: Application
    Filed: April 21, 2006
    Publication date: October 26, 2006
    Inventors: Takashige Baba, Kazuhide Horimoto
  • Publication number: 20060059456
    Abstract: In network setting, when setting inputted from a management terminal is inputted into management agent of a CPU blade, the management agent performs network setting to a device driver of the CPU blade, performs setting of NIC to the device driver of the CPU blade and creates network setting information required for a port of an Ethernet switch module unit connected to the NIC to notify the same to a management module unit. The management module unit recognizes a port of Ethernet switch module units which corresponds to the NIC and performs network setting to the port of the Ethernet switch module based on the acquired network configuration information. Accordingly, a technology capable of easily performing the setting of network in a composite computer apparatus in a short time is provided.
    Type: Application
    Filed: August 3, 2005
    Publication date: March 16, 2006
    Inventor: Takashige Baba
  • Publication number: 20050267963
    Abstract: A method is provided for efficiently managing the connection of processor modules and input/output interface modules at a drastically reduced cost. A management server searches IFT and ST tables after receiving an instruction from the system management server to connect an input/output interface module to a processor, creates a condition list requested by the input/output interface module, and selects an input/output interface matching the condition list JL from an unassigned input/output interface module management table UNT. The management server next instructs the input/output interface switch to connect the processor with the selected input/output interface. The management server instructs the input/output device management server and the network management server to setup a connection utilizing the selected input/output interface, and rewrites the tables UNT and SPT.
    Type: Application
    Filed: February 9, 2005
    Publication date: December 1, 2005
    Inventors: Takashige Baba, Toshiaki Tarui, Yoshifumi Takamoto
  • Publication number: 20050097402
    Abstract: In a storage device including plural disk controllers, the invention reduces time required for failure recovery when a failure occurs in the disk controllers. The storage device includes n (n>2, where n is an integer) disk controllers. The disk controller includes a cache memory. Data of the cache memory is copied to another cache memory. When a failure occurs in the disk controller, data not written to a disk of the data copied to the cache memory is transferred to further another cache memory.
    Type: Application
    Filed: June 28, 2004
    Publication date: May 5, 2005
    Inventor: Takashige Baba
  • Publication number: 20040218665
    Abstract: A signal transmit-receive device that reduces the number of high-speed signal lines required for connecting a transmitting circuit group and a receiving circuit group and for running a loopback test on a signal transmit-receive device for signal communication, and reduces installation costs and power consumption. The new loopback test circuit uses an error detecting circuit within the transmitting circuit IC, a test signal producing circuit within the receiving circuit IC, and a wiring for transmitting error information from the transmitting circuit to the receiving circuit. The error detecting circuit compares a test signal pattern defined in advance by a first communication device and a received signal pattern to detect errors. The test signal producing circuit produces a test signal pattern defined in advance by the first communication device, and can invert any bits of the test signal pattern, based on error information.
    Type: Application
    Filed: December 5, 2002
    Publication date: November 4, 2004
    Inventors: Takashige Baba, Tatsuya Saito, Hiroki Yamashita, Yusuke Takeuchi, Satoru Isomura
  • Publication number: 20040109476
    Abstract: A signal communication apparatus of a clock reproduction system in which clock signals are extracted from each of parallel data signals for redigitizing each of the data signals. The apparatus includes a reference clock signal generating circuit which is comprised of a clock extraction circuit for extracting a clock signal from each of a plurality of bits of received data signals, and a clock signal selection circuit for selecting one of the extracted clock signals. Alternatively, the reference clock signal generating circuit may be comprised of a data signal selection circuit for selecting one of a plurality of received data signals, and a clock extraction circuit for extracting a clock signal from the selected bit. Based on the resultant reference clock signal, clock signals are obtained that are phase-adjusted for redigitizing each bit of the received data signals.
    Type: Application
    Filed: July 30, 2003
    Publication date: June 10, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Takashige Baba, Tatsuya Saito, Masayoshi Yagyu, Shigeo Oomae