Patents by Inventor Takasi Togasaki

Takasi Togasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5959363
    Abstract: A semiconductor device comprising a wiring circuit board and a semiconductor chip mounted through a bump electrode on the circuit board, a space between the circuit board and the semiconductor chip as well as a periphery of the semiconductor chip being encapsulated with a resin containing a filler. The resin is constituted by a first resin disposed in a region surrounded by bump electrodes positioned on the outermost periphery of the semiconductor chip, and by a second resin disposed in a region not surrounded by bump electrodes positioned on the outermost periphery of the semiconductor chip, the first and second resins being distinct from each other in at least one feature selected from a content, a maximum particle diameter and an average particle diameter of the filler.
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: September 28, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Yamada, Takasi Togasaki, Masayuki Saito, Soichi Honma, Miki Mori, Kazuki Tateyama
  • Patent number: 5864178
    Abstract: A semiconductor device comprising a wiring circuit board and a semiconductor chip mounted through a bump electrode on the circuit board, a space between the circuit board and the semiconductor chip as well as a periphery of the semiconductor chip being encapsulated with a resin containing a filler. The resin is constituted by a first resin disposed in a region surrounded by bump electrodes positioned on the outermost periphery of the semiconductor chip, and by a second resin disposed in a region not surrounded by bump electrodes positioned on the outermost periphery of the semiconductor chip, the first and second resins being distinct from each other in at least one feature selected from a content, a maximum particle diameter and an average particle diameter of the filler.
    Type: Grant
    Filed: January 3, 1996
    Date of Patent: January 26, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Yamada, Takasi Togasaki, Masayuki Saito, Soichi Honma, Miki Mori, Kazuki Tateyama
  • Patent number: 5821627
    Abstract: An electronic circuit device includes a substrate, a wiring layer formed on the surface of the substrate and essentially consisting of at least one metal selected from the group consisting of gold, copper, tin, and aluminum, a bump formed on the wiring layer and essentially consisting of at least one metal selected from the group consisting of gold, copper, and aluminum, and a micro electronic element formed on the bump, wherein solid-phase diffusion bonding is performed at least either between the wiring layer and the bump or between the bump and an electrode of the micro electronic element.
    Type: Grant
    Filed: November 5, 1997
    Date of Patent: October 13, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Miki Mori, Yukio Kizaki, Takaaki Yasumoto, Koji Yamakawa, Masayuki Saito, Tatsuro Uchida, Takasi Togasaki, Takashi Yebisuya, Taijun Murakami
  • Patent number: 5684677
    Abstract: An electronic circuit device comprising a printed wiring board having a major surface and pads provided on the major surface of the printed wiring board, a plurality of electrodes provided partly on at least one major surface of the leadless component and partly on sides of the leadless component, a plurality of bumps provided on the pads, providing a gap between the major surface of the printed wiring board and the major surface of the leadless component, and electrically connecting those parts of the electrodes which are provided on the major surface of the leadless component to the pads, and a plurality of electrically conductive members integral with the bumps, extending from the bumps to those parts of the electrodes which are provided on the sides of the leadless component.
    Type: Grant
    Filed: July 29, 1996
    Date of Patent: November 4, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuro Uchida, Takashi Yebisuya, Miki Mori, Masayuki Saito, Takasi Togasaki, Yukio Kizaki
  • Patent number: 5448114
    Abstract: A semiconductor device contains a semiconductor chip and a circuit board. The chip has a first surface at which the main region is formed. On the surface, a plurality of chip electrodes and a perimeter electrode surrounding the chip electrodes are formed. Bumps and a wall member made of solder metal are formed on the chip electrodes and frame-shaped electrode, respectively. The circuit board has a first surface facing the first surface of the chip. On the first surface of the circuit board, a plurality of board electrodes and a perimeter electrode are placed so as to correspond to the chip electrodes and the perimeter electrode. In a state where the chip and the board face each other, heat treatment is performed to connect the bumps and wall member to the board simultaneously by reflow. The wall member connects the chip to the board while surrounding the main region and the bumps continuously, to form essentially a closed space between the chip and the board.
    Type: Grant
    Filed: February 15, 1995
    Date of Patent: September 5, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: You Kondoh, Masayuki Saito, Takasi Togasaki