Abstract: An abnormality detection circuit includes: a plurality of voltage dividing circuits; a first selector configured to select and output one of a plurality of outputs of the plurality of voltage dividing circuits; a first comparator configured to compare an output of the first selector with a reference voltage; and a first detector configured to detect an abnormality based on an output of the first comparator, wherein the selection of the first selector is switched in synchronization with a vertical synchronization signal or a horizontal synchronization signal of a liquid crystal display device.

Abstract: An abnormality detection circuit includes: a plurality of voltage dividing circuits; a first selector configured to select and output one of a plurality of outputs of the plurality of voltage dividing circuits; a first comparator configured to compare an output of the first selector with a reference voltage; and a first detector configured to detect an abnormality based on an output of the first comparator, wherein the selection of the first selector is switched in synchronization with a vertical synchronization signal or a horizontal synchronization signal of a liquid crystal display device.

Abstract: An abnormality detection circuit includes: a plurality of voltage dividing circuits; a first selector configured to select and output one of a plurality of outputs of the plurality of voltage dividing circuits; a first comparator configured to compare an output of the first selector with a reference voltage; and a first detector configured to detect an abnormality based on an output of the first comparator, wherein the selection of the first selector is switched in synchronization with a vertical synchronization signal or a horizontal synchronization signal of a liquid crystal display device.

Abstract: An abnormality detection circuit includes: a plurality of voltage dividing circuits; a first selector configured to select and output one of a plurality of outputs of the plurality of voltage dividing circuits; a first comparator configured to compare an output of the first selector with a reference voltage; and a first detector configured to detect an abnormality based on an output of the first comparator, wherein the selection of the first selector is switched in synchronization with a vertical synchronization signal or a horizontal synchronization signal of a liquid crystal display device.

Abstract: An abnormality detection circuit includes: a plurality of voltage dividing circuits; a first selector configured to select and output one of a plurality of outputs of the plurality of voltage dividing circuits; a first comparator configured to compare an output of the first selector with a reference voltage; and a first detector configured to detect an abnormality based on an output of the first comparator, wherein the selection of the first selector is switched in synchronization with a vertical synchronization signal or a horizontal synchronization signal of a liquid crystal display device.

Abstract: An abnormality detection circuit includes: a plurality of voltage dividing circuits; a first selector configured to select and output one of a plurality of outputs of the plurality of voltage dividing circuits; a first comparator configured to compare an output of the first selector with a reference voltage; and a first detector configured to detect an abnormality based on an output of the first comparator, wherein the selection of the first selector is switched in synchronization with a vertical synchronization signal or a horizontal synchronization signal of a liquid crystal display device.

Abstract: A source driver 130 includes a first latch 131 outputting a first data signal D1(1) having multiple bits (e.g., eight bits), a second latch 132 outputting a second data signal D2(1) by latching the first data signal D1(1) in a plurality of steps in units of one or more bits, a DAC 133 converting the second data signal D2(1) into an analog signal A(1), and an amplifier 134 receiving the analog signal A(1) to output a source signal S(1). The second latch 132 latches the first data signal D1(1), e.g., one bit at every clock, one bit at every plurality of clocks, a plurality of bits at every clock, or a plurality of bits at every plurality of clocks.

Abstract: An abnormality detection circuit includes: a plurality of voltage dividing circuits; a first selector configured to select and output one of a plurality of outputs of the plurality of voltage dividing circuits; a first comparator configured to compare an output of the first selector with a reference voltage; and a first detector configured to detect an abnormality based on an output of the first comparator, wherein the selection of the first selector is switched in synchronization with a vertical synchronization signal or a horizontal synchronization signal of a liquid crystal display device.

Abstract: A source driver 130 includes a first latch 131 outputting a first data signal D1(1) having multiple bits (e.g., eight bits), a second latch 132 outputting a second data signal D2(1) by latching the first data signal D1(1) in a plurality of steps in units of one or more bits, a DAC 133 converting the second data signal D2(1) into an analog signal A(1), and an amplifier 134 receiving the analog signal A(1) to output a source signal S(1). The second latch 132 latches the first data signal D1(1), e.g., one bit at every clock, one bit at every plurality of clocks, a plurality of bits at every clock, or a plurality of bits at every plurality of clocks.

Abstract: An abnormality detection circuit includes: a plurality of voltage dividing circuits; a first selector configured to select and output one of a plurality of outputs of the plurality of voltage dividing circuits; a first comparator configured to compare an output of the first selector with a reference voltage; and a first detector configured to detect an abnormality based on an output of the first comparator, wherein the selection of the first selector is switched in synchronization with a vertical synchronization signal or a horizontal synchronization signal of a liquid crystal display device.

Abstract: A parallel interface is disclosed. The parallel interface of the present disclosure includes an input unit configured to input, in parallel, a plurality of predetermined data signals and a clock signal; an output unit configured to output, in parallel, the predetermined data signals in synchronization with the clock signal; and a plurality of transmission lines disposed between the input unit and the output unit and configured to transmit, in parallel, the predetermined data signals and the clock signal, wherein the transmission lines are configured with a wiring pattern in which the transmission lines have different electrical lengths and an equal electrical capacitance.

Abstract: A clock signal generating circuit includes: an oscillator having a trimming function of arbitrarily adjusting an oscillation frequency of a first clock signal generated by the oscillator depending on trimming data; and a trimming data modulation part configured to dynamically change a reference trimming data for adjusting the oscillation frequency of the first clock signal to generate modulation trimming data, and output the modulation trimming data, as the trimming data, to the oscillator.

Abstract: A clock signal generating circuit includes: an oscillator having a trimming function of arbitrarily adjusting an oscillation frequency of a first clock signal generated by the oscillator depending on trimming data; and a trimming data modulation part configured to dynamically change a reference trimming data for adjusting the oscillation frequency of the first clock signal to generate modulation trimming data, and output the modulation trimming data, as the trimming data, to the oscillator.

Abstract: A parallel interface is disclosed. The parallel interface of the present disclosure includes an input unit configured to input, in parallel, a plurality of predetermined data signals and a clock signal; an output unit configured to output, in parallel, the predetermined data signals in synchronization with the clock signal; and a plurality of transmission lines disposed between the input unit and the output unit and configured to transmit, in parallel, the predetermined data signals and the clock signal, wherein the transmission lines are configured with a wiring pattern in which the transmission lines have different electrical lengths and an equal electrical capacitance.

Abstract: A semiconductor device includes: a trimming object circuit configured to use a trimming circuit to adjust an output based on a trimming value; and a trimming value setting circuit configured to set the trimming value. The trimming value setting circuit includes: a register configured to volatilely store a pseudo-trimming value set with reference to a trimming table such that an output value of the trimming object circuit becomes equal to a target value; a trimming value storage configured to non-volatilely store a final trimming value, wherein the final trimming value is set by correcting the pseudo-trimming value with reference to a trimming value correction table such that the output value of the trimming object circuit, which is obtained based on the pseudo-trimming value, becomes equal to the target value; and a selector configured to select one of the pseudo-trimming value and the final trimming value as the trimming value.

Abstract: An image forming system according to an embodiment of the present invention includes an air cleaner for cleaning air, an image forming apparatus that is settable to a mode for economizing power, and a control unit that causes a display unit of the air cleaner to display an operating state of the image forming apparatus when the image forming apparatus is set to the mode for economizing power. An image forming system according to another embodiment of the present invention includes an image forming apparatus that prints an image on recording paper, an air cleaner that is for cleaning air, and is integrally attached to the image forming apparatus via a support member, and supported above the image forming apparatus by the support member, and a control unit that causes a display unit of the air cleaner to display an operating state of the image forming apparatus.

Abstract: An image compression circuit 1 of the invention includes an image calculator 11, a compression-system decision unit 12, and a compression processor 13. Compression-system decision unit 12 determines a variation of pieces of image data of four adjacent pixels based on a variation in luminance Y of the pixels or variations in luminance Y and saturation S of the pixels, compresses the image data into image data of one or two pixels (RGB 888 and RGB 787) expressed by an RGB color space having a small quantization error in the case of the small variation of the pieces of image data, and compresses the image data into data including the luminances of the four adjacent pixels and pieces of image data of two pixels (YCbCr 422) expressed by a YCbCr color space having a large quantization error in the case of the large variation of the pieces of image data.

Abstract: A semiconductor device includes: a trimming object circuit configured to use a trimming circuit to adjust an output based on a trimming value; and a trimming value setting circuit configured to set the trimming value. The trimming value setting circuit includes: a register configured to volatilely store a pseudo-trimming value set with reference to a trimming table such that an output value of the trimming object circuit becomes equal to a target value; a trimming value storage configured to non-volatilely store a final trimming value, wherein the final trimming value is set by correcting the pseudo-trimming value with reference to a trimming value correction table such that the output value of the trimming object circuit, which is obtained based on the pseudo-trimming value, becomes equal to the target value; and a selector configured to select one of the pseudo-trimming value and the final trimming value as the trimming value.

Abstract: An image forming system is provided with an Image Forming Operation Unit, an Air Cleaning Operation Unit, a power source, and a Control Unit. The Control Unit has a coordinated OFF control function of coordinating a first power supply OFF control for turning off power supply from the power source to the Image Forming Operation Unit and a second power supply OFF control for turning off power supply from the power source to the Air Cleaning Operation Unit, and the coordinated OFF control function is configured to execute the second power supply OFF control when a preset time period elapses after executing the first power supply OFF control. Also, in the image forming system, an air cleaning operation of an air cleaning apparatus is stopped when an image forming apparatus is set to an a night mode or when a fixed time period elapses after the night mode is set. The air cleaning operation of the air cleaning apparatus is restarted when the image forming apparatus is resumed from the night mode.

Abstract: An image compression circuit 1 of the invention includes an image calculator 11, a compression-system decision unit 12, and a compression processor 13. Compression-system decision unit 12 determines a variation of pieces of image data of four adjacent pixels based on a variation in luminance Y of the pixels or variations in luminance Y and saturation S of the pixels, compresses the image data into image data of one or two pixels (RGB 888 and RGB 787) expressed by an RGB color space having a small quantization error in the case of the small variation of the pieces of image data, and compresses the image data into data including the luminances of the four adjacent pixels and pieces of image data of two pixels (YCbCr 422) expressed by a YCbCr color space having a large quantization error in the case of the large variation of the pieces of image data.