Patents by Inventor Takatomo Enoki

Takatomo Enoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8687968
    Abstract: A vector sum phase shifter includes a 90° phase shifter (1) which generates an in-phase signal (VINI) and a quadrature signal (VINQ) from an input signal (VIN), a four-quadrant multiplier (2I) which changes the amplitude of the in-phase signal (VINI) based on a control signal (CI), a four-quadrant multiplier (2Q) which changes the amplitude of the quadrature signal (VINQ) based on a control signal (CQ), a combiner (3) which combines the in-phase signal (VINI) and the quadrature signal (VINQ), and a control circuit (4). The control circuit (4) includes a voltage generator which generates a reference voltage, and a differential amplifier which outputs the difference signal between a control voltage (VC) and the reference voltage as the control signal (CI, CQ). The differential amplifier performs an analog operation of converting the control voltage (VC) into the control signal (CI, CQ) similar to a sine wave or a cosine wave.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: April 1, 2014
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Hideyuki Nosaka, Munehiko Nagatani, Shogo Yamanaka, Kimikazu Sano, Koichi Murata, Kiyomitsu Onodera, Takatomo Enoki
  • Patent number: 8687973
    Abstract: A voltage generator (400) includes a resistor ladder including resistors (4000-4008) which divide a supplied voltage to generate a plurality of reference voltages, a resistor (4009) provided between a power supply voltage (VCC) and one terminal of the resistor ladder, and a resistor (4010) provided between a power supply voltage (VEE) and the other terminal of the resistor ladder.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: April 1, 2014
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Hideyuki Nosaka, Munehiko Nagatani, Shogo Yamanaka, Kimikazu Sano, Koichi Murata, Kiyomitsu Onodera, Takatomo Enoki
  • Publication number: 20110236027
    Abstract: A voltage generator (400) includes a resistor ladder including resistors (4000-4008) which divide a supplied voltage to generate a plurality of reference voltages, a resistor (4009) provided between a power supply voltage (VCC) and one terminal of the resistor ladder, and a resistor (4010) provided between a power supply voltage (VEE) and the other terminal of the resistor ladder.
    Type: Application
    Filed: August 12, 2009
    Publication date: September 29, 2011
    Inventors: Hideyuki Nosaka, Munehiko Nagatani, Shogo Yamanaka, Kimikazu Sano, Koichi Murata, Kiyomitsu Onodera, Takatomo Enoki
  • Publication number: 20110150495
    Abstract: A vector sum phase shifter includes a 90° phase shifter (1) which generates an in-phase signal (VINI) and a quadrature signal (VINQ) from an input signal (VIN), a four-quadrant multiplier (2I) which changes the amplitude of the in-phase signal (VINI) based on a control signal (CI), a four-quadrant multiplier (2Q) which changes the amplitude of the quadrature signal (VINQ) based on a control signal (CQ), a combiner (3) which combines the in-phase signal (VINI) and the quadrature signal (VINQ), and a control circuit (4). The control circuit (4) includes a voltage generator which generates a reference voltage, and a differential amplifier which outputs the difference signal between a control voltage (VC) and the reference voltage as the control signal (CI, CQ). The differential amplifier performs an analog operation of converting the control voltage (VC) into the control signal (CI, CQ) similar to a sine wave or a cosine wave.
    Type: Application
    Filed: August 12, 2009
    Publication date: June 23, 2011
    Inventors: Hideyuki Nosaka, Munehiko Nagatani, Shogo Yamanaka, Kimikazu Sano, Koichi Murata, Kiyomitsu Oncodera, Takatomo Enoki
  • Patent number: 6144048
    Abstract: A Schottky barrier layer in separate regions between a source electrode and a gate electrode and between a drain electrode and the gate electrode is completely covered with an etching stopper layer. The gate electrode is separated from a cap layer.
    Type: Grant
    Filed: December 23, 1999
    Date of Patent: November 7, 2000
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Tetsuya Suemitsu, Takatomo Enoki
  • Patent number: 6090649
    Abstract: A Schottky barrier layer in separate regions between a source electrode and a gate electrode and between a drain electrode and the gate electrode is completely covered with an etching stopper layer. The gate electrode is separated from a cap layer.
    Type: Grant
    Filed: December 23, 1999
    Date of Patent: July 18, 2000
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Tetsuya Suemitsu, Takatomo Enoki
  • Patent number: 5151757
    Abstract: A heterojunction field-effect transistor includes a first electron transit channel formation semiconductor layer formed on a substrate and consisting of a compound semiconductor, a first electron supply semiconductor layer formed on the first electron transit channel formation semiconductor layer and consisting of a compound semiconductor, a gate electrode, a source electrode, and a drain electrode formed on the first electron supply semiconductor layer, and a second electron transit channel formation semiconductor layer formed between the substrate and the first electron transit channel formation semiconductor layer.
    Type: Grant
    Filed: October 24, 1991
    Date of Patent: September 29, 1992
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Takatomo Enoki, Naoteru Shigekawa, Kunihiro Arai
  • Patent number: 4694564
    Abstract: In the manufacture of a Schottky gate field effect transistor, an insulating film is deposited on the main surface of a semiconductor substrate and is then selectively removed to form therein a window through which the substrate surface region for forming an active layer is exposed to a space in which the gate will ultimately be provided. A metal which forms a Schottky junction between it and the semiconductor of the active layer and can be removed by anisotropic etching and a metal which can be used as a mask for the etching of the above metal are deposited in layers on the insulating film and the substrate surface exposed through the window. The overlying metal layer thus deposited is planarized to leave in the window alone. The underlying metal layer is selectively removed by anisotropic etching through the overlying metal layer remaining in the window, thus forming a gate electrode made up of the overlying and underlying metal layers.
    Type: Grant
    Filed: July 21, 1986
    Date of Patent: September 22, 1987
    Inventors: Takatomo Enoki, Kimiyoshi Yamasaki, Kuniki Ohwada