Patents by Inventor Takatoshi Deguchi

Takatoshi Deguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7576001
    Abstract: A semiconductor device manufacturing method for suppressing surface roughness of a Low-k insulating film during etching. In a laminated structure comprising a layer having formed thereon a lower copper wiring, a SiC film and a SiOC film, a via and an upper copper wiring are formed as follows. The SiOC film is etched to form a via hole opening that reaches the SiC film and then to form wiring grooves that communicate with the opening. Thereafter, when the SiC film on the bottom of the opening is etched to form a via hole, a deposited film of etching products is formed on surfaces of the via hole and the wiring grooves. This deposited film allows planarization of the SiOC film surface, which is exposed to plasma, formed thereon the via hole and the wiring grooves. Subsequently, formation of a Ta film and burying of plating copper are performed.
    Type: Grant
    Filed: July 18, 2005
    Date of Patent: August 18, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Takatoshi Deguchi
  • Publication number: 20060199376
    Abstract: A semiconductor device manufacturing method for suppressing surface roughness of a Low-k insulating film during etching. In a laminated structure comprising a layer having formed thereon a lower copper wiring, a SiC film and a SiOC film, a via and an upper copper wiring are formed as follows. The SiOC film is etched to form a via hole opening that reaches the SiC film and then to form wiring grooves that communicate with the opening. Thereafter, when the SiC film on the bottom of the opening is etched to form a via hole, a deposited film of etching products is formed on surfaces of the via hole and the wiring grooves. This deposited film allows planarization of the SiOC film surface, which is exposed to plasma, formed thereon the via hole and the wiring grooves. Subsequently, formation of a Ta film and burying of plating copper are performed.
    Type: Application
    Filed: July 18, 2005
    Publication date: September 7, 2006
    Applicant: FUJITSU LIMITED
    Inventor: Takatoshi Deguchi
  • Patent number: 7060635
    Abstract: The present invention provides a method of manufacturing a semiconductor device which includes a step of forming a laminated film for pattern formation on a substrate, in which the laminated film for pattern formation includes an innermost layer, an inner layer and a surface layer, an extinction coefficient k of the innermost layer is 0.3 or more, and an extinction coefficient k of the inner layer is 0.12 or more. It also provides a method of forming a pattern which includes a step of forming a laminated film for pattern formation on a substrate, in which the laminated film for pattern formation includes an innermost layer, an inner layer and a surface layer, an extinction coefficient k of the innermost layer is 0.3 or more, and an extinction coefficient k of the inner layer is 0.12 or more.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: June 13, 2006
    Assignee: Fujitsu Limited
    Inventors: Akihiko Otoguro, Satoshi Takechi, Takatoshi Deguchi
  • Patent number: 7049221
    Abstract: After forming an Si3N4 film as a hard mask for a wiring, a lower resin film for filling and planarizing a level difference thereon is formed. Next, an SOG film is formed on the lower resin film, and a resist mask on which a via hole pattern is formed is formed thereon. The SOG film is etched by using the resist mask as a mask. The lower resin film is etched by using the SOG film as a mask, and at the same time, the resist mask is removed. Then, a triple layer hard mask is etched by using the lower resin film as a mask. Consequently, a via hole pattern is formed on these films, and the SOG film is simultaneously removed. According to this method, the resist mask having a pattern as designed can be obtained, and a micro pattern with high precision can be obtained.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: May 23, 2006
    Assignee: Fujitsu Limited
    Inventor: Takatoshi Deguchi
  • Publication number: 20040137711
    Abstract: After forming an Si3N4 film as a hard mask for a wiring, a lower resin film for filling and planarizing a level difference thereon is formed. Next, an SOG film is formed on the lower resin film, and a resist mask on which a via hole pattern is formed is formed thereon. The SOG film is etched by using the resist mask as a mask. The lower resin film is etched by using the SOG film as a mask, and at the same time, the resist mask is removed. Then, a triple layer hard mask is etched by using the lower resin film as a mask. Consequently, a via hole pattern is formed on these films, and the SOG film is simultaneously removed. According to this method, the resist mask having a pattern as designed can be obtained, and a micro pattern with high precision can be obtained.
    Type: Application
    Filed: October 29, 2003
    Publication date: July 15, 2004
    Inventor: Takatoshi Deguchi
  • Publication number: 20040033444
    Abstract: The present invention provides a method of manufacturing a semiconductor device which includes a step of forming a laminated film for pattern formation on a substrate, in which the laminated film for pattern formation includes an innermost layer, an inner layer and a surface layer, an extinction coefficient k of the innermost layer is 0.3 or more, and an extinction coefficient k of the inner layer is 0.12 or more. It also provides a method of forming a pattern which includes a step of forming a laminated film for pattern formation on a substrate, in which the laminated film for pattern formation includes an innermost layer, an inner layer and a surface layer, an extinction coefficient k of the innermost layer is 0.3 or more, and an extinction coefficient k of the inner layer is 0.12 or more.
    Type: Application
    Filed: June 25, 2003
    Publication date: February 19, 2004
    Inventors: Akihiko Otoguro, Satoshi Takechi, Takatoshi Deguchi