Abstract: An information processing apparatus includes a packet preprocessing unit configured to generate a packet process request when a packet is received; a CPU core configured to process the packet in response to the packet process request; a hardware element configured to generate a message including information identifying a predetermined event, in response to the predetermined event occurring in accordance with the processing of the packet, the hardware element being provided in the CPU core; and a message recording unit configured to record the message generated by the hardware element together with a count value of a timer.

Abstract: A performance profiling apparatus includes: a plurality of counters provided for a routine included in a program; a storage section configured to store an instruction of the program and an identification information indicating the routine of the program; a processor configured to read the instruction from the storage section and to execute a process according to the instruction; and a counter controller configured to, at the time of reading the instruction of the processor, receive the identification information of the instruction which is output from the storage section with the instruction and to instruct a first counter designated by the identification information to count up.

Abstract: A program profiler circuit includes: a stack having a first storage region for stacking, when an instruction to call a subroutine is detected, a head address of the subroutine and for unstacking a lastly stacked head address when a restoration instruction to return to a source from which the subroutine is called is detected; a matching determining unit that has a plurality of second storage regions in which head addresses of subroutines are registered and is configured to output region information indicating a second storage region having registered therein a head address that matches the head address lastly stacked by the stack processing unit; and an accumulator that has a plurality of accumulation regions corresponding to the plurality of second storage regions and is configured to increment with a predetermined value to a value stored in an accumulation region corresponding to the region information output from the matching determining unit.

Abstract: In a multicore system in which a plurality of CPUs each including a cache memory share one main memory, a write buffer having a plurality of stages of buffers each holding data to be written to the main memory and an address of a write destination is provided between the cache memory and the main memory, and at the time of a write to the write buffer from the cache memory, an address of a write destination and the addresses stored in the buffers are compared, and when any of the buffers has an agreeing address, data is overwritten to this buffer, and the buffer is logically moved to a last stage.

Abstract: An information processing apparatus includes a packet preprocessing unit configured to generate a packet process request when a packet is received; a CPU core configured to process the packet in response to the packet process request; a hardware element configured to generate a message including information identifying a predetermined event, in response to the predetermined event occurring in accordance with the processing of the packet, the hardware element being provided in the CPU core; and a message recording unit configured to record the message generated by the hardware element together with a count value of a timer.

Abstract: A cache controller receives a reference request from a CPU executing a program in which information indicative of a reference request specifying in shared memory, an area not having an update request and information indicative of a snoop reference request are distinguished from one another. When the reference request specifying an area not having the update request is received, the cache controller acquires from the shared memory and without performing a snoop process, information stored in the specified area. The cache controller stores the information acquired from the shared memory to the cache memory of the CPU executing the program.

Abstract: When an invalidation request is inputted from another processing device, a cache controller registers a set of an invalidation request address which the invalidation request has and an identifier of the other processing device which outputted the invalidation request in an invalidation history table. When a central processing unit attempts to read data at a first address not stored in a cache memory, if the first address is registered in the invalidation history table, the cache controller outputs a coherent read request containing the first address to the other processing device indicated by the identifier of the other processing device which outputted the invalidation request corresponding to the first address, or if the first address is not registered in the invalidation history table, the cache controller outputs a coherent read request containing the first address to all other processing devices.

Abstract: A performance profiling apparatus includes: a plurality of counters provided for a routine included in a program; a storage section configured to store an instruction of the program and an identification information indicating the routine of the program; a processor configured to read the instruction from the storage section and to execute a process according to the instruction; and a counter controller configured to, at the time of reading the instruction of the processor, receive the identification information of the instruction which is output from the storage section with the instruction and to instruct a first counter designated by the identification information to count up.

Abstract: In a multicore system in which a plurality of CPUs each including a cache memory share one main memory, a write buffer having a plurality of stages of buffers each holding data to be written to the main memory and an address of a write destination is provided between the cache memory and the main memory, and at the time of a write to the write buffer from the cache memory, an address of a write destination and the addresses stored in the buffers are compared, and when any of the buffers has an agreeing address, data is overwritten to this buffer, and the buffer is logically moved to a last stage.

Abstract: An arithmetic processing circuit includes a plurality of arithmetic processing units, a plurality of selector circuits each configured to select one of a plurality of power supplies that are fewer than the arithmetic processing units and to connect the selected power supply to a corresponding one of the arithmetic processing units, and a power supply control circuit configured to variably control an output voltage of at least one of the plurality of power supplies.

Abstract: A cache memory is operated in a write through system, and an operation to be performed when a cache mishit occurs is performed when corresponding data is not stored in the cache memory, or only when an error occurs although there is the data. Then, a bit indicating that a soft error has occurred before is set in the cache memory, and when the bit indicates “1” and if an error has occurred again, it is determined that a hardware error has occurred, and an interrupt is generated in the CPU. The bit is to be reset at time intervals sufficiently shorter than the frequency at which it is considered that a soft error occurs.

Abstract: A cache memory is operated in a write through system, and an operation to be performed when a cache mishit occurs is performed when corresponding data is not stored in the cache memory, or only when an error occurs although there is the data. Then, a bit indicating that a soft error has occurred before is set in the cache memory, and when the bit indicates “1” and if an error has occurred again, it is determined that a hardware error has occurred, and an interrupt is generated in the CPU. The bit is to be reset at time intervals sufficiently shorter than the frequency at which it is considered that a soft error occurs.

Abstract: An information bit and a redundant bit at addresses of memory determined by a random number are both read without receiving error detection or error correction, the bit at a bit position determined by a random number is inverted, and the bit-inverted data is written to the same address of the same memory. The number of bits (one bit, two or more bits, etc.) to be inverted is set appropriately on the basis of what types of errors are to be caused in a simulated manner.

Abstract: According to the present invention, in order to simultaneously realize high-speed transmission suppressing signal reflection and reduction of power consumption, a bidirectional transmission circuit, in which a plurality of sending/receiving elements send and receive signals via a transmission bus, is constructed so that, when a first sending/receiving element operates as a sending side, a first control unit sets a connection of the transmission bus to a first termination voltage source via a first terminating resistor by a first switch to off and a second control unit sets a connection of the transmission bus to a second termination voltage source via a second terminating resistor by a second switch to on.

Abstract: When a user indicates a point on a display screen of a computer using a pen sensor, first the display screen is divided into a plurality of areas and the areas are displayed by mutually different colors or brightnesses. The plurality of colors or brightnesses displayed are scanned by the pen sensor and the colors or brightnesses detected by the light receiver to judge in which area the indicated point is located. Next, the judged area is further divided into a plurality of areas which are displayed by mutually different colors or brightnesses. Next, a routine similar to the above is successively repeated to narrow down the area in which the point indicated by the pen sensor is located and finally determine the position of the point, that is, the XY coordinates on the display screen.

Abstract: An information processing apparatus includes a tuner receiving a signal according to a received broadcast, a first processing part performing a desired processing on the signal supplied from the tuner, converting the signal into a first signal of a given format, and outputting the first signal, a second processing part converting the signal supplied from the tuner into a second signal of the given format and outputting the second signal, and an output part selectively outputting one of the first and second signals. The first and second processing parts are startable independently of each other.

Abstract: A storing part stores image data of an input image signal; and a control part detects a resolution of the image data from a synchronization signal which is in synchronization with the input image signal, and, controls timing of reading the image data from the storing part according to the thus-detected resolution. The control part detects periods of a horizontal synchronization signal and vertical synchronization signal which are in synchronization with the input image signal, determines a magnification for an image to be output, from a horizontal synchronization interval and a vertical synchronization interval of the image to be output, and the periods of the horizontal synchronization signal and vertical synchronization signal which are in synchronization with the input image signal; and controls the timing of reading the image data from said storing part according to the thus-determined magnification.

Abstract: A method and apparatus for converting a digital video signal, to a signal having a resolution that matches a display device, by using simple hardware alone. When a digital video signal is input together with a data enable (DE) signal and a dot clock (DCLK) signal, the number of clocks of the DCLK signal generated during an active period of the DE signal is counted and, based on the thus counted number of clocks, the resolution of the input video image is identified; then, based on the resolution thus identified, the pixel density of the input video signal is converted so as to form a video signal having a resolution that matches the display device. Alternatively, the resolution of the input video signal may be identified by counting the number of pulses of the DE signal generated during one vertical synchronization period.

Abstract: When a user indicates a point on a display screen of a computer using a pen sensor, first the display screen is divided into a plurality of areas and the areas are displayed by mutually different colors or brightnesses. The plurality of colors or brightnesses displayed are scanned by the pen sensor and the colors or brightnesses detected by the light receiver to judge in which area the indicated point is located. Next, the judged area is further divided into a plurality of areas which are displayed by mutually different colors or brightnesses. Next, a routine similar to the above is successively repeated to narrow down the area in which the point indicated by the pen sensor is located and finally determine the position of the point, that is, the XY coordinates on the display screen.

Abstract: An information processing apparatus includes a tuner receiving a signal according to a received broadcast, a first processing part performing a desired processing on the signal supplied from the tuner, converting the signal into a first signal of a given format, and outputting the first signal, a second processing part converting the signal supplied from the tuner into a second signal of the given format and outputting the second signal, and an output part selectively outputting one of the first and second signals. The first and second processing parts are startable independently of each other.