Abstract: In a duplicated arrangement for an ATM switching system, first and second store-and-forward buffers are provided for storing and forwarding an ATM cell stream and first and second counters are responsive to a timing signal for producing a first cell count and a second cell count representative of counts of cells stored in the first and second store-and-forward buffers, respectively. A detector is provided for detecting a difference between the first and second cell counts. A buffer controller controls the second store-and-forward buffer in accordance with the difference so that the count of cells in the second buffer approaches the count of cells in the first buffer. A switching circuit normally couples the ATM cell stream forwarded from the first buffer to an output port of the ATM switching system and couples the ATM cell stream forwarded from the second buffer, instead of from the first buffer, to the output port in response to a switching command signal.

Abstract: A buffer control circuit is arranged for each of a master board and a slave board having FIFO buffers corresponding to each output port. Each of the buffer control circuits is arranged on the boards in a bit-slice structure. The buffer control circuit on the side of the master board transmits a synchronizing control signal to the corresponding buffer control circuit on the side of the slave boards. The buffer control circuit resets the corresponding FIFO buffer to synchronize the boards, when routing control signals indicate empty cell, or output ports to which the cells are not addressed and an empty FIFO buffer 14 exists. A monitoring trigger is periodically input to the buffer control circuit 21 at predetermined intervals, and the number of cells in the FIFO buffer on each of the boards are compared for each destinations at the time of inputting the monitoring trigger.

Abstract: In a policing arrangement for an ATM network, every incoming cell is stored in a cell buffer and a virtual path identifier (VPI) contained in the cell is extracted and translated to a corresponding one of a set of threshold values. Policing circuits of a matrix array are connected column by column for transferring a VPI in accordance with a read/write control circuit. Each policing circuit of the first column is uniquely responsive to a VPI of a particular value for storing the extracted VPI into a bridge memory, and this column has a greater number of policing circuits than any of the other columns of the array. In each column of the array, at least one of the policing circuits includes a cell counter for incrementing a cell count value in response to the VPI of every incoming cell and decrementing the cell count in response to a VPI read out of the bridge memory of the policing circuit.

Abstract: In a monitor system in a digital communication apparatus including communication processing blocks on transmission paths of digital data, test data inserting units and data monitor units are arranged such that a monitor interval for the monitor operation in a block overlaps with a monitor period for the monitor operation between adjacent blocks in each processing block. As a result, there is no unmonitored interval in each processing block, thereby achieving a complete monitor operation.

Abstract: In a cross-connect apparatus for use in selectively connecting a plurality of input transmission paths to a plurality of output transmission paths, each of the input and the output transmission paths is divided into first through m-th groups each of which is composed of first through n-th transmission paths, first through m-th elementary switch modules are located between the input and the output transmission paths, n in number, of the first through the m-th groups and are connected to a connection switch module through first to m-th input internal path groups each of which is composed of n internal paths and which are extended into first through m-th switch units each of which has input terminals, n(m-1) in number, and output terminals, n in number, where n and m are natural numbers. An i-th one of the switch units in the connection switch module is connected to the input path groups, (m-1) in number, except an i-th internal path group, where i is a natural number between unity and m, both inclusive.

Abstract: A policing control apparatus having a cell input terminal receiving asynchronous transmission communication network cells; a policing circuit coupled to the input terminal for policing transmission of cells according to policing information; a cell output terminal from the policing circuit for outputting policed cells; a count memory in the policing circuit for storing a count value of the cells supplied to the policing circuit and for supplying the count value as the policing information; and a self-diagnosing circuit for monitoring problems and abnormalities of stored contents in the count memory and outputting an alarm upon detection of a problem or abnormality.

Abstract: In an ATM switching network, ATM (asynchronous transfer mode) self-routing switches are interconnected by facilities carrying STM-N (synchronous transport modules level N) signals. At each inlet of an ATM self-routing switch, an STM overhead is removed from each frame of an incoming STM-N signal to create a vacant interval and the frame is converted according to ATM cell format into a series of data ATM cells, and an idle ATM cell is derived from the vacant interval. A supervisory bit sequence is inserted to the payload field of the idle ATM cell to produce a supervisory ATM cell, and the data and supervisory ATM cells are sent into the ATM switch. At each outlet of the switch, the bit sequence of the supervisory ATM cell is checked to evaluate the quality of the ATM switch and a series of data ATM cells is then converted into an STM-N signal according to STM-N frame format.

Abstract: On time division multiplexing first through N-th input signals, each having a bit rate V to represent successive ATM cells, a multiplexing section (12, 13') multiplexes the first through the N-th input signals and a dummy input signal into a time division multiplexed signal having another bit rate V.times.(N+1) and comprising first through N-th multiplexed cells and a dummy multiplexed cell. The first through the N-th and the dummy multiplexed cells are derived from the first through the N-th and the dummy input signals, respectively. A controller (16') successively writes valid cells of the first through the N-th multiplexed cells in an FIFO memory (15) as written cells at a writing rate equal to the bit rate V.times.(N+1) for a writing time interval defined by the first through the N-th multiplexed cells and reads the written cells from the FIFO memory in a first-in first-out order as a read-out signal at a reading rate equal to the bit rate V.times.

Abstract: In a routing system having a plurality of external input ports and a plurality of external output ports, a switch network having a plurality of internal input ports and a plurality of internal output ports, an input section between the external input ports and the internal input ports, an output section between the internal output ports and the external output ports, and a control section connected to the switch network and the input section, an input port number which may be assigned to each of the external input ports is arranged in a routing information field of a transmission path signal by an input port number setter included in the input section. The input port number is memorized in a discarded cell memory of the control section together with an internal output port number which is assigned to the internal output ports and which is derived from a routing table along with a header. On occurrence of a discarded cell, the cause of discard can be analyzed by the use of the input port number and the header.