Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes an electrically rewritable nonvolatile memory, a grounding pad, a first power supply pad, a second power supply pad, a voltage reduction circuit, and a first pump circuit. A first power supply is supplied to the first power supply pad. A second power supply, a voltage of which is higher than that of the first power supply is supplied to the second power supply pad. The voltage reduction circuit reduces the second power supply, generates a first voltage lower than that of the second power supply, and supplies the first voltage to the nonvolatile memory. The first pump circuit generates a voltage higher than that of the second power supply on the basis of the first power supply, and supplies the second voltage to the nonvolatile memory.

Abstract: According to one embodiment, a power supply circuit, which generates a power supply voltage which is applied to a memory cell array including a plurality of memory cells disposed at intersections between a plurality of word lines and a plurality of bit lines, comprises a first boost circuit configured to boost an input voltage, a first voltage step-down circuit having an input connected to an output of the first boost circuit, and a voltage control circuit configured to control the first boost circuit and the first voltage step-down circuit. The voltage control circuit is configured to generate, not via the first voltage step-down circuit, a voltage which is boosted by the first boost circuit, when a first voltage is transferred to a non-selected memory cell.

Abstract: A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M<N) of the word lines close to the i-th word line pass through a region above the gate electrode by a first level interconnection without passing over the impurity diffused layers.