Patents by Inventor Takatoshi Nomura

Takatoshi Nomura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220319491
    Abstract: A vehicle sound generation device includes a controller that generates a sound signal representing a sound and sets the localization of the sound, and left and right front speakers and left and right rear speakers that output sounds corresponding to the sound signals for which localization has been set by the controller, in which the controller sets the localization of the sounds based on the change amounts (such as the pitch rate, the torque change amount, the roll rate, and steering angular speed) per unit time of the physical quantities correlated with a driving operation by the driver of the vehicle so that the sound image of at least part (low frequency component) of frequency components of the sound is located toward the wheel where the ground load is increasing according to the driving operation.
    Type: Application
    Filed: February 22, 2022
    Publication date: October 6, 2022
    Applicant: Mazda Motor Corporation
    Inventors: Yukifusa HATTORI, Shuhei OTSUKI, Ryuichi YAMADA, Takatoshi NOMURA
  • Patent number: 11411494
    Abstract: A first current mirror circuit is provided between a first transistor and a power supply line to return a current that flows to the first transistor. A second current mirror circuit returns an output current from the first current mirror circuit, and generates a starting current. An inverter has an input connected to a node, and an output connected to a control terminal of the first transistor. A first current source generates a first current when a power supply voltage has exceeded a first threshold value. A third current mirror circuit draws a current proportional to the first current from an input side of the second current mirror circuit. A second current source supplies a second current to the node when the power supply voltage has exceeded a second threshold value.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: August 9, 2022
    Assignee: ROHM Co., LTD.
    Inventors: Naohiro Nomura, Takatoshi Manabe
  • Patent number: 10290759
    Abstract: A perovskite photoelectric conversion element includes a light transmitting substrate 11, on a front surface of which light is made incident, an oxide porous layer 13, formed on a rear surface of the light transmitting substrate 11 and with metal oxide particles 12 connected in a network, a metal porous layer 15, formed on a rear surface of the oxide porous layer 13 and with metal particles 14 connected in a network, a porous insulating layer 17, formed on a rear surface of the metal porous layer 15, a first electrode layer 18, formed on and across an entirety of a rear surface of the porous insulating layer 17, a second electrode layer 19, connected to the metal porous layer 15 and formed at a portion different from the first electrode layer 18 in a state of being insulated from the first electrode layer 18, and perovskite 20.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: May 14, 2019
    Assignees: FUJICO CO., LTD., KYUSHU INSTITUTE OF TECHNOLOGY, CKD CORPORATION
    Inventors: Shuzi Hayase, Tingli Ma, Hideaki Nagayoshi, Daishiro Nomura, Takatoshi Nomura
  • Publication number: 20180261708
    Abstract: A perovskite photoelectric conversion element includes a light transmitting substrate 11, on a front surface of which light is made incident, an oxide porous layer 13, formed on a rear surface of the light transmitting substrate 11 and with metal oxide particles 12 connected in a network, a metal porous layer 15, formed on a rear surface of the oxide porous layer 13 and with metal particles 14 connected in a network, a porous insulating layer 17, formed on a rear surface of the metal porous layer 15, a first electrode layer 18, formed on and across an entirety of a rear surface of the porous insulating layer 17, a second electrode layer 19, connected to the metal porous layer 15 and formed at a portion different from the first electrode layer 18 in a state of being insulated from the first electrode layer 18, and perovskite 20.
    Type: Application
    Filed: March 8, 2018
    Publication date: September 13, 2018
    Applicants: FUJICO CO., LTD., KYUSHU INSTITUTE OF TECHNOLOGY, CKD CORPORATION
    Inventors: Shuzi Hayase, Tingli Ma, Hideaki Nagayoshi, Daishiro Nomura, Takatoshi Nomura
  • Patent number: 9747132
    Abstract: A multi-core processor includes a plurality of former-stage cores that perform parallel processing using a plurality of pipelines covering a plurality of stages. In the pipelines, the former-stage cores perform stages ending with an instruction decode stage; stages starting with an instruction execution stage are executed by a latter-stage core. A dynamic load distribution block refers to decode results in the instruction decode stage and controls to assign the latter-stage core with a latter-stage-needed decode result being a decode result whose processing needs to be executed in the latter-stage core.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: August 29, 2017
    Assignee: DENSO CORPORATION
    Inventors: Hirofumi Yamamoto, Takeshi Kondo, Shinichirou Taguchi, Takatoshi Nomura, Daihan Wang, Tomoyoshi Funazaki, Yukoh Matsumoto
  • Publication number: 20140346512
    Abstract: In a semiconductor integrated circuit device, a target chip, a test chip, and an electronic device are incorporated in a package. A signal terminal of the target chip is a target terminal and to be subjected to a test. The test chip has a test mechanism for allowing the test to be performed through an external terminal exposed outside the package. In a product operation mode where the semiconductor integrated circuit device operates as a product, the electronic device is connected to the target terminal. The test chip includes a common wire connected to the test terminal, a first terminal connected to the target terminal, a first switch for opening and closing a connection between the common wire and the first terminal, a second terminal connected to the electronic device, and a second switch for opening and closing a connection between the first terminal and the second terminal.
    Type: Application
    Filed: May 15, 2014
    Publication date: November 27, 2014
    Applicant: DENSO CORPORATION
    Inventor: Takatoshi NOMURA
  • Publication number: 20140317380
    Abstract: A multi-core processor includes a plurality of former-stage cores that perform parallel processing using a plurality of pipelines covering a plurality of stages. In the pipelines, the former-stage cores perform stages ending with an instruction decode stage; stages starting with an instruction execution stage are executed by a latter-stage core. A dynamic load distribution block refers to decode results in the instruction decode stage and controls to assign the latter-stage core with a latter-stage-needed decode result being a decode result whose processing needs to be executed in the latter-stage core.
    Type: Application
    Filed: April 4, 2014
    Publication date: October 23, 2014
    Applicant: DENSO CORPORATION
    Inventors: Hirofumi YAMAMOTO, Takeshi KONDO, Shinichirou TAGUCHI, Takatoshi NOMURA, Daihan WANG, Tomoyoshi FUNAZAKI, Yukoh MATSUMOTO
  • Patent number: 8288321
    Abstract: Provides a new non-oxide system compound material superconductor as an alternative of the perovskite type copper oxides superconductor. Layered compounds which are represented by chemical formula AF(TM)Pn (wherein, A is at least one selected from a group consisting of the second family elements in the long form periodic table, F is a fluorine ion, TM is at least one selected from a group of transition metal elements consisting of Fe, Ru, Os, Ni, Pd, and Pt, and Pn is at least one selected from a group consisting of the fifteenth family elements in the long form periodic table), having a crystal structure of ZrCuSiAs type (space group P4/nmm) and which become superconductors by doping trivalent cations or divalent anions.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: October 16, 2012
    Assignee: Japan Science and Technology Agency
    Inventors: Hideo Hosono, Hiroshi Yanagi, Toshio Kamiya, Satoru Matsuishi, Sungwng Kim, Seok Gyu Yoon, Hidenori Hiramatsu, Masahiro Hirano, Takatoshi Nomura, Yoichi Kamihara
  • Publication number: 20110111965
    Abstract: Provides a new non-oxide system compound material superconductor as an alternative of the perovskite type copper oxides superconductor. Layered compounds which are represented by chemical formula AF(TM)Pn (wherein, A is at least one selected from a group consisting of the second family elements in the long form periodic table, F is a fluorine ion, TM is at least one selected from a group of transition metal elements consisting of Fe, Ru, Os, Ni, Pd, and Pt, and Pn is at least one selected from a group consisting of the fifteenth family elements in the long form periodic table), having a crystal structure of ZrCuSiAs type (space group P4/nmm) and which become superconductors by doping trivalent cations or divalent anions.
    Type: Application
    Filed: July 9, 2009
    Publication date: May 12, 2011
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Hideo Hosono, Hiroshi Yanagi, Toshio Kamiya, Satoru Matsuishi, Sungwng Kim, Seok Gyu Yoon, Hidenori Hiramatsu, Masahiro Hirano, Takatoshi Nomura, Yoichi Kamihara
  • Publication number: 20110045985
    Abstract: A superconductor which comprises a new compound composition substituting for perovskite copper oxides. The superconductor is characterized by comprising a compound which is represented by the chemical formula A(TM)2Pn2 [wherein A is at least one member selected from the elements in Group 1, the elements in Group 2, or the elements in Group 3 (Sc, Y, and the rare-earth metal elements); TM is at least one member selected from the transition metal elements Fe, Ru, Os, Ni, Pd, or Pt; and Pn is at least one member selected from the elements in Group 15 (pnicogen elements)] and which has an infinite-layer crystal structure comprising (TM)Pn layers alternating with metal layers of the element (A).
    Type: Application
    Filed: February 20, 2009
    Publication date: February 24, 2011
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Hideo Hosono, Hiroshi Yanagi, Toshio Kamiya, Satoru Matsuishi, Sungwng Kim, Seok Gyu Yoon, Hidenori Hiramatsu, Masahiro Hirano, Yoichi Kamihara, Takatoshi Nomura