Abstract: One embodiment includes a vertical n-channel power MOSFET for an output stage and a horizontal p-channel MOSFET for controlling the vertical n-channel power MOSFET are disposed on a single semiconductor substrate. The horizontal p-channel MOSFET has Psd (a p+-type source region and a p+-type drain region) formed in a self-aligning manner at a gate electrode. The Psd has p+-type diffusion regions disposed therein causing the Psd to partially have a high impurity concentration. The p+-type diffusion regions are connected to respective metal wiring layers through contact holes that are formed by ion implantation concurrently with a p+-type diffusion region of the vertical n-channel power MOSFET and that have a width narrower than conventional contact holes. In this way, contact properties can be improved between the metal wiring layer and a semiconductor portion and size reductions can be achieved.

Abstract: One embodiment includes a vertical n-channel power MOSFET for an output stage and a horizontal p-channel MOSFET for controlling the vertical n-channel power MOSFET are disposed on a single semiconductor substrate. The horizontal p-channel MOSFET has Psd (a p+-type source region and a p+-type drain region) formed in a self-aligning manner at a gate electrode. The Psd has p+-type diffusion regions disposed therein causing the Psd to partially have a high impurity concentration. The p+-type diffusion regions are connected to respective metal wiring layers through contact holes that are formed by ion implantation concurrently with a p+-type diffusion region of the vertical n-channel power MOSFET and that have a width narrower than conventional contact holes. In this way, contact properties can be improved between the metal wiring layer and a semiconductor portion and size reductions can be achieved.

Abstract: A method of forming a device in each of vertical trench gate MOSFET region and control lateral planar gate MOSFET region of a semiconductor substrate is disclosed. A trench is formed in the substrate in the vertical trench gate MOSFET region, a first gate oxide film is formed along the internal wall of the trench, and the trench is filled with a polysilicon film. A LOCOS oxide film is formed in a region isolating the devices. A second gate oxide film is formed on the substrate in the lateral planar gate MOSFET region. Advantages are that number of steps is suppressed, the gate threshold voltage of an output stage MOSFET is higher than the gate threshold voltage of a control MOSFET, the thickness of the LOCOS oxide film does not decrease, and no foreign object residue remains inside the trench.

Abstract: A temperature sensor circuit is provided that facilitates preventing a too-high overshooting voltage from occurring at an output terminal when a power supply is connected to the temperature sensor circuit. The temperature sensor circuit includes a short-circuiting device, disposed in parallel to depletion mode NMOS, that short-circuits the drain and source of depletion mode NMOS when a power supply is connected; and delay device that transmits a signal for short-circuiting the drain and source of depletion mode NMOS for a certain period from the time point of power supply connection to short-circuiting device for preventing the voltage at output terminal of temperature sensor circuit from overshooting.

Abstract: A temperature sensor circuit is provided that facilitates preventing a too-high overshooting voltage from occurring at an output terminal when a power supply is connected to the temperature sensor circuit. The temperature sensor circuit includes a short-circuiting device, disposed in parallel to depletion mode NMOS, that short-circuits the drain and source of depletion mode NMOS when a power supply is connected; and delay device that transmits a signal for short-circuiting the drain and source of depletion mode NMOS for a certain period from the time point of power supply connection to short-circuiting device for preventing the voltage at output terminal of temperature sensor circuit from overshooting.