Abstract: The optimization of a refresh cycle is carried out in harmony with the error occurrence state in the memory with the presence of a normal patrol controlling section controlling a normal patrol operation that patrols the memory; an additional patrol controlling section controlling an additional patrol operation that patrols, if a first error in the memory is detected during the normal patrol operation, an error occurring area in which the first error occurs and which is included in the memory; a measuring section (15) measuring, if a second error is detected in the error occurring area during the additional patrol operation, an error frequency representing information of error in the error occurring area; and a refresh cycle adjusting section adjusting the refresh cycle in accordance with the error frequency measured by the measuring section.

Abstract: When a single error of data is detected by an ECC circuit, a cycle adjusting unit provided on a memory board shortens a refresh cycle T1 of a refresh request generating unit to T2 and causes a patrol controlling unit to intensively carry out an error patrol of an error-occurred address at a cycle T3, which is slightly longer than the changed refresh cycle T2. If an error is not detected for more than a predetermined period of time after the error patrol is started, the error patrol is stopped. Furthermore, if a single error is not detected for more than a predetermined period of time after the error patrol is stopped, the shortening of the refresh cycle is cancelled and returned to the original cycle.

Abstract: A data transfer apparatus in which, in a failure state such that an error packet is received at a reception end, the error packet is returned and is recorded in the transmission end, the error packet is analyzed and an error bit is identified at the transmission end, and data transmission/reception units are initialized and restarted in order to recover from the failure state.

Abstract: A method of adjusting a phase includes generating phase adjustment patterns corresponding to transmission circuits by performing a serial-to-parallel conversion on a fundamental phase adjustment pattern in a transmission side circuit; transmitting, by the transmission circuits, transmission signals including the phase adjustment patterns; generating phase adjustment patterns corresponding to receiving circuits corresponding to the transmission circuits by performing the serial-to-parallel conversion on the fundamental phase adjustment pattern in a receiving side circuit; receiving, by the receiving circuits, the transmission signals using a reception clock signal; comparing signal patterns included in the transmission signals with the phase adjustment patterns and output comparison results; and adjusting a phase of the reception clock signal based on the comparison results.

Abstract: The optimization of a refresh cycle is carried out in harmony with the error occurrence state in the memory with the presence of a normal patrol controlling section controlling a normal patrol operation that patrols the memory; an additional patrol controlling section controlling an additional patrol operation that patrols, if a first error in the memory is detected during the normal patrol operation, an error occurring area in which the first error occurs and which is included in the memory; a measuring section (15) measuring, if a second error is detected in the error occurring area during the additional patrol operation, an error frequency representing information of error in the error occurring area; and a refresh cycle adjusting section adjusting the refresh cycle in accordance with the error frequency measured by the measuring section.

Abstract: A data transfer apparatus in which, in a failure state such that an error packet is received at a reception end, the error packet is returned and is recorded in the transmission end, the error packet is analyzed and an error bit is identified at the transmission end, and data transmission/reception units are initialized and restarted in order to recover from the failure state.

Abstract: When a single error of data is detected by an ECC circuit, a cycle adjusting unit provided on a memory board shortens a refresh cycle T1 of a refresh request generating unit to T2 and causes a patrol controlling unit to intensively carry out an error patrol of an error-occurred address at a cycle T3, which is slightly longer than the changed refresh cycle T2. If an error is not detected for more than a predetermined period of time after the error patrol is started, the error patrol is stopped. Furthermore, if a single error is not detected for more than a predetermined period of time after the error patrol is stopped, the shortening of the refresh cycle is cancelled and returned to the original cycle.

Abstract: A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control unit includes an invalidation command issuing unit that issues a cache line invalidation command to all reference designations stored in the directory memory in cache lines. Thus the device process time can be shortened by reducing the frequency that cache invalidation commands are issued from the cache memory.

Abstract: A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control unit includes an invalidation command issuing unit that issues a cache line invalidation command to all reference designations stored in the directory memory in cache lines. Thus the device process time can be shortened by reducing the frequency that cache invalidation commands are issued from the cache memory.

Abstract: A plurality of processors, each with caches provided for a plurality of processor modules and a local storage in which a main storage is distributed and arranged are mutually connected through an internal snoop bus. The processor modules are mutually connected through a second system bus. By using two separate buses, cache coherence operations within a processor group is kept separate from cache coherence operations outside the processor group.

Abstract: An asynchronous access system for a computer system includes processing modules performing processes, at least one shared system memory module, and a system bus connecting the processing modules and the shared system memory module. Each of the processing modules includes a processor, a plurality of buffers coupled to the processor and to the system bus, and a controlling unit for writing data from the plurality of processors into the shared system memory module. Data is written into the shared system memory module by a processor generating write instructions to write data via the plurality of buffers and the system bus. The controlling unit controls the writing such that one writing instruction writes data into a plurality of buffers, then transfers the data to the shared system memory module via the system bus, with another writing instruction writing additional data into another plurality of buffers and transferring the additional data to the shared system memory module.

Abstract: An exclusive control system is provided in a system having a memory module and a plurality of processing modules sharing the memory module, each of the plurality of processing modules exclusively accessing the memory module while prohibiting other processing modules from accessing the memory module. The exclusive control system includes a determination unit for determining whether or not a process executed in response to an access request from a processor module among the plurality of processing modules is normally completed in the memory module, and a retry unit for, when the determination unit determines that the process executed in response to the access request is not normally completed, retrying the process while maintaining a state in which other processing modules are prohibited from accessing the memory module.

Abstract: A message control system for a data communication system which takes the form of a loosely coupled multiprocessing system in which a plurality of processing modules respectively having a memory unit are coupled to each other via a system bus. In the message control system, each processing module (10, 40) includes a central processing unit (11, 41), a memory unit (12, 42) and a connection unit (13, 43). The connection unit (13, 43) includes at least a logical transmitting port (21, 51) for transmitting a message, a logical receiving port (22, 53) for receiving a message, a transmission system connecting unit (23), a reception system connecting unit (24), a transmitting side fault generation monitoring unit (25) and a receiving side fault generation monitoring unit (26).