Abstract: A three-dimensional (3D) NAND memory structure may include material layers arranged in a vertical stack including alternating horizontal insulating layers and wordline layers. The material layers may be etched to form a landing pad. A vertical wordline may extend through one or more of the horizontal wordline layers beneath the landing pad. The vertical wordline may be conductively connected to a top horizontal wordline, and the vertical wordline may be insulated from any of the horizontal wordlines that the vertical wordline extends through beneath the top horizontal wordline. A liner may also be formed over a top horizontal wordline at the landing pad.

Abstract: In a semiconductor device producing method according to one embodiment, an insulating film containing silicon is formed on a semiconductor substrate, a resist is deposited on the insulating film, the resist is patterned into a predetermined pattern, and the insulating film is processed by a dry etching treatment in which gas containing C, F, Br, H, and O is used with the resist having the predetermined pattern as a mask. A deposited film in which C and Br are coupled is produced on the resist.

Abstract: In a semiconductor device producing method according to one embodiment, an insulating film containing silicon is formed on a semiconductor substrate, a resist is deposited on the insulating film, the resist is patterned into a predetermined pattern, and the insulating film is processed by a dry etching treatment in which gas containing C, F, Br, H, and O is used with the resist having the predetermined pattern as a mask. A deposited film in which C and Br are coupled is produced on the resist.

Abstract: A substrate cleaning method performing cleaning of a surface of a substrate after a pattern on the substrate is formed by plasma etching, includes: a by-product removal process removing a by-product by exposing the substrate to an HF gas atmosphere; and a residual fluorine removal process removing fluorine remaining on the substrate by turning cleaning gas containing hydrogen gas and chemical compound gas containing carbon and hydrogen as constituent elements into plasma to act on the substrate.

Abstract: A method of manufacturing a semiconductor memory device of an embodiment includes: after forming a first interconnection layer and a memory cell layer above a semiconductor substrate, forming first lines by forming first grooves extending in first direction; forming a thin film on the side walls of the first grooves; forming a stack structure by filling an interlayer insulating film in the first grooves; forming a second interconnection layer above the stack structure; forming second lines by forming second grooves extending in second direction; removing the thin film exposed at bottom of the second grooves; and forming columnar memory cells by removing the memory cell layer exposed at bottom of the second grooves. The thin film has higher etching rate than the interlayer insulating film, and is removed prior to portions of the memory cell layer adjoining the thin film.

Abstract: A semiconductor device is provided with a conductor wire and a fuse wire formed in an insulating film over a semiconductor substrate, a first under-pad-wire insulating film formed above the insulating film, a second under-pad-wire insulating film formed on the first under-pad-wire insulating film, a pad wire formed in an area above the conductive wire, in the first and second under-pad-wire insulating films and an opening formed by leaving a part of the first under-pad-wire insulating film in an area above the fuse wire, in the first and second under-pad-wire insulating films, wherein the second under-pad-wire insulating film comprises an element different from that of the first under-pad-wire insulating film.

Abstract: A semiconductor device is provided with a conductor wire and a fuse wire formed in an insulating film over a semiconductor substrate, a first under-pad-wire insulating film formed above the insulating film, a second under-pad-wire insulating film formed on the first under-pad-wire insulating film, a pad wire formed in an area above the conductive wire, in the first and second under-pad-wire insulating films and an opening formed by leaving a part of the first under-pad-wire insulating film in an area above the fuse wire, in the first and second under-pad-wire insulating films, wherein the second under-pad-wire insulating film comprises an element different from that of the first under-pad-wire insulating film.

Abstract: A method of manufacturing a semiconductor device includes subjecting a semiconductor wafer, which includes a copper layer formed above a semiconductor substrate and covered with an insulating film, to a dry etching using a fluorocarbon gas to partially remove the insulating film, thereby at least partially exposing a surface of the copper layer. The copper layer, the surface of which is at least partially exposed is subjected to a nitrogen plasma treatment. The semiconductor wafer having the nitrogen plasma-treated copper layer is exposed to atmosphere, and then the semiconductor wafer is subjected to a surface treatment.

Abstract: A method of manufacturing a semiconductor device includes subjecting a semiconductor wafer, which includes a copper layer formed above a semiconductor substrate and covered with an insulating film, to a dry etching using a fluorocarbon gas to partially remove the insulating film, thereby at least partially exposing a surface of the copper layer. The copper layer, the surface of which is at least partially exposed is subjected to a nitrogen plasma treatment. The semiconductor wafer having the nitrogen plasma-treated copper layer is exposed to atmosphere, and then the semiconductor wafer is subjected to a surface treatment.

Abstract: Disclosed is a method of manufacturing a semiconductor device, which comprises the steps of forming an insulating film or a metal film on a surface of a semiconductor substrate, forming at least two kinds of mask on a surface of the insulating film or the metal film, and performing a plurality of etching works to the insulating film or the metal film in conformity with the various kinds of mask.

Abstract: Disclosed is a method of manufacturing a semiconductor device, which comprises the steps of forming an insulating film or a metal film on a surface of a semiconductor substrate, forming at least two kinds of mask on a surface of the insulating film or the metal film, and performing a plurality of etching works to the insulating film or the metal film in conformity with the various kinds of mask.

Abstract: The present invention is to provide an electrostatic chucking device having improved heat conductivity and at the same time increased adsorption area and improved adsorptity as well as having no uneveness on the wafer-provided face. The electrostatic chucking device of the present invention comprises a metal base, an adhesive layer, an electrode layer comprising a metal-deposited or metal-plated layer, and an electrically insulating layer possessing a face for providing a substance to be adhered by suction, laminated thereon in this order.

Abstract: The present invention is to provide an electrostatic chucking device having improved heat conductivity and at the same time increased adsorption area and improved adsorptity as well as having no uneveness on the wafer-provided face. The electrostatic chucking device of the present invention comprises a metal base, an adhesive layer, an electrode layer comprising a metal-deposited or metal-plated layer, and an electrically insulating layer possessing a face for providing a substance to be adhered by suction, laminated thereon in this order.

Abstract: A plasma etching apparatus has a lower electrode for supporting a semiconductor wafer in a processing room, an upper electrode opposite to the lower electrode, and an RF power supply for applying an RF power across the upper and lower electrodes. An SiN layer as an underlayer having a shoulder portion, and an SiO.sub.2 layer covering the SiN layer are disposed on the wafer. A contact hole is formed in the SiO.sub.2 layer by etching so as to expose the shoulder portion of the SiN layer. A processing gas contains C.sub.4 F.sub.8 and CO. To set the etching selection ratio of SiO.sub.2 /SiN, the discharge duration of each part of the processing gas is used as a parameter. The progress of dissociation of C.sub.4 F.sub.8 is controlled by selecting the discharge duration. The discharge duration is determined by the residence time of each part of the processing gas and the application time of an RF power.

Abstract: A dry etching method which includes supplying a workpiece having an oxide portion or a nitride portion into a processing vessel, keeping said workpiece at temperatures not higher than 0.degree. C. within said processing vessel, supplying an etching gas including a first gas containing a halogen element and a second gas containing carbon having an oxidation number of less than 4 and oxygen to a region in the vicinity of the workpiece while keeping the temperature the workpiece at a level not higher than 0.degree. C., and forming a plasma of said etching gas for etching the oxide portion or the nitride portion of the workpiece with said plasma.

Abstract: A dry etching method by a plasma etching forms a mask pattern, having an opening up to 1 .mu.m width on a silicon oxide layer formed on a silicon substrate. The substrate is laced into a reactive chamber having an etching gas introducing means and fluorocarbon gas and hydrogen gas as the etching gas are introduced such that a ratio of the hydrogen gas to the gas mixture satisfies 50% to 80%. The plasma is generated, and by using the plasma etching, the silicon oxide layer is etched according to the mask pattern to form an opening having an aspect ratio of more than 1 in the silicon oxide layer.

Abstract: A magnetron plasma etching apparatus comprises a suscepter serving as an electrode on which a silicon wafer is mounted. A carbon ring having an outer diameter larger than the diameter of the wafer and an electrical resistance lower than that of the wafer, is arranged around the suscepter. The carbon ring is electrically connected to the suscepter. The carbon ring improves uniformity of etching of the wafer.