Abstract: A semiconductor cell for photomask data verification is disclosed that is provided in a semiconductor chip having a semiconductor integrated circuit and used for verifying photomask data of the semiconductor chip obtained by performing arithmetic processing on layout data of the semiconductor integrated circuit. The semiconductor cell for photomask data verification has the photomask data obtained by performing the arithmetic processing on the layout data of the semiconductor integrated circuit and is electrically separated from the semiconductor integrated circuit.

Abstract: A semiconductor cell for photomask data verification is disclosed that is provided in a semiconductor chip having a semiconductor integrated circuit and used for verifying photomask data of the semiconductor chip obtained by performing arithmetic processing on layout data of the semiconductor integrated circuit. The semiconductor cell for photomask data verification has the photomask data obtained by performing the arithmetic processing on the layout data of the semiconductor integrated circuit and is electrically separated from the semiconductor integrated circuit.

Abstract: A semiconductor storing device can access a plurality of addresses simultaneously without increasing a circuit area and a wiring area. A row of memory cells is selected by two stages of a word line and a division word line. An address is specified by X[i:0], Y[j:0], and Z[k:0]. Two roots of selection signals are alternately provided to division word line selectors arranged in one memory array. One of two roots of the selection signals is enabled to select the division word line selector. Eight roots of the selection signals in the entire semiconductor storing device are enabled to access eight addresses simultaneously.

Abstract: A semiconductor storing device can access a plurality of addresses simultaneously without increasing a circuit area and a wiring area. A row of memory cells is selected by two stages of a word line and a division word line. An address is specified by X[i:0], Y[j:0], and Z[k:0]. Two roots of selection signals are alternately provided to division word line selectors arranged in one memory array. One of two roots of the selection signals is enabled to select the division word line selector. Eight roots of the selection signals in the entire semiconductor storing device are enabled to access eight addresses simultaneously.

Abstract: A semiconductor memory apparatus allows accessing data stored therein using a plurality of different addressing types such as bit slice type and word slice type. The semiconductor memory apparatus includes memory elements having a plurality of memory cell arrays and corresponding column gates that control connections between the memory cell arrays and a first sense amp, a first write buffer, a second sense amp, and a second write buffer in response to an external signal designating the addressing type and the reading or writing of data.

Abstract: A semiconductor memory apparatus allows accessing data stored therein using a plurality of different addressing types such as bit slice type and word slice type. The semiconductor memory apparatus includes memory elements having a plurality of memory cell arrays and corresponding column gates that control connections between the memory cell arrays and a first sense amp, a first write buffer, a second sense amp, and a second write buffer in response to an external signal designating the addressing type and the reading or writing of data.

Abstract: A processor used in a synchronous data transfer system in which a processor, a direct memory access controller and peripheral devices are connected to a memory via the same bus, includes a detection circuit for detecting whether the processor uses the bus in a forthcoming cycle, and a control circuit having a first terminal for acknowledging a request signal from the direct memory access controller requesting a use of the bus, only when the detection circuit detects that the processor does not use the bus in the forthcoming cycle, wherein the control circuit discards a right to use the bus and outputs a response signal to the direct memory access controller indicating that the processor grants the right to use the bus to the direct memory access controller, when the request signal is acknowledged.