Patents by Inventor Takayasu Kawamura

Takayasu Kawamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4667215
    Abstract: In manufacturing a GTO, a silicon wafer is cut away along one of the crystal planes indicated by {100} in Miller indices, and the burried gate or the current channels are so arranged on the crystal plane that at least one longitudinal direction thereof is substantially in parallel with at least one of axes indicated by <100> on condition that the inner product of the plane vector and the axis vector is zero. In the GTO thus manufactured, it is possible to minimize the crystal defect density on the crystal plane and thus to realize the GTOs having uniform turned-on voltage, in particular, while increasing the controllable current markedly.
    Type: Grant
    Filed: May 17, 1985
    Date of Patent: May 19, 1987
    Assignee: Kabushiki Kaisha Meidensha
    Inventors: Takayasu Kawamura, Yasuhide Hayashi
  • Patent number: 4651188
    Abstract: In manufacturing a GTO, a silicon wafer is cut away along one of the crystal planes indicated by {n11} in Miller indices, and the burried gate or the current channels are so arranged on the crystal plane that at least one longitudinal direction thereof is substantially in parallel with at least one of axes indicated by <2nn> on condition that the inner product of the plane vector and the axis vector is zero. In the GTO thus manufactured, it is possible to minimize the crystal defect density on the crystal plane and thus to realize the GTOs having uniform turned-on voltage, in particular, while increasing the controllable current markedly.
    Type: Grant
    Filed: May 3, 1985
    Date of Patent: March 17, 1987
    Assignee: Kabushiki Kaisha Meidensha
    Inventors: Yasuhide Hayashi, Takayasu Kawamura