Abstract: A solid-state imaging device includes a plurality of pixel circuits arranged in rows and columns; and a relief unit which includes N signal lines and n pixel circuits among the plurality of pixel circuits, N being an integer greater than or equal to 3, n being an integer less than or equal to N. Each of the n pixel circuits is connected to a group of at least two signal lines out of the N signal lines, and selectively outputs a pixel signal to one of the at least two signal lines included in the group; and n groups corresponding to the n pixel circuits have mutually different combinations of signal lines, the n groups each being the group.

Abstract: A solid-state imaging apparatus includes a pixel circuit, a detection and selection circuit, and an AD conversion circuit. The pixel circuit outputs a plurality of pixel signals corresponding to mutually different gains or sensitivities. The detection and selection circuit compares one or more of the plurality of pixel signals with a reference value to generate a signal selection signal that instructs selection of a pixel signal among the plurality of pixel signals. The detection and selection circuit includes a sample and hold circuit that holds the plurality of pixel signals, and selects at least one pixel signal among the plurality of pixel signals held in the sample and hold circuit based on the signal selection signal. The detection and selection circuit is arranged in a stage before the AD conversion circuit that AD converts the at least one pixel signal selected.

Abstract: A solid-state imaging apparatus includes a plurality of high-sensitivity pixels that are arranged in a matrix, and perform a photoelectric conversion at a predetermined sensitivity; a plurality of low-sensitivity pixels that are arranged in a matrix in gaps between the plurality of high-sensitivity pixels, and perform a photoelectric conversion at a lower sensitivity than the predetermined sensitivity; and a signal processor that generates a pixel signal by (i) detecting a difference signal between a signal from the plurality of high-sensitivity pixels and a signal from the plurality of low-sensitivity pixels, and (ii) correcting the signal from the plurality of high-sensitivity pixels using the difference signal.

Abstract: A solid-state imaging device includes: a pixel including a photoelectric converter that generates a charge and a charge accumulator that converts the charge into a voltage; a controller that causes the pixel to perform exposure in a first exposure mode and convert the charge into the voltage with a first gain to output a first pixel signal, and causes the pixel to perform exposure in a second exposure mode and convert the charge into the voltage with a second gain to output a second pixel signal, the second exposure mode being shorter in exposure time than the first exposure mode, and the second gain being lower than the first gain; and a signal processor that synthesizes the second pixel signal after amplification and the first pixel signal.

Abstract: A solid-state imaging device includes: a pixel array unit in which a plurality of pixels are arranged in rows and columns; a plurality of column signal lines which are provided in one-to-one correspondence with pixel columns; a column processor including a plurality of column AD circuits provided in one-to-one correspondence with the plurality of column signal lines; a power supply variation detector which is connected to a power supply wire through which a power supply voltage is transmitted to each of the pixels, and which detects, in correspondence with pixel rows, power supply variation components attributed to variations in the power supply voltage; and a power supply variation corrector which corrects, for each of the pixel rows, a pixel signal detected by the column processor, using the power supply variation components detected by the power supply variation detector.

Abstract: A solid-state imaging apparatus includes a pixel array, a column processor, and a test signal generating circuit that generates a first digital signal for testing purposes. The test signal generating circuit generates the first digital signal within one horizontal scanning period. The column processor converts a first analog signal, that is converted from the first digital signal, to a second digital signal within the one horizontal scanning period.

Abstract: An imaging device having a pixel including a photoelectric converter that converts incident light into charges, and a reset transistor having a first source, a first drain and a first gate, one of the first source and the first drain coupled to the photoelectric converter. The imaging device further including first voltage generating circuity that generates a first voltage; second voltage generating circuity that generates a second voltage, the second voltage generating circuity being different from the first voltage generating circuity; and first switching circuity that causes either the first voltage generating circuity or the second voltage generating circuity to selectively couple to the other of the first source and the first drain of the reset transistor.

Abstract: A solid-state imaging apparatus includes a plurality of high-sensitivity pixels that are arranged in a matrix, and perform a photoelectric conversion at a predetermined sensitivity; a plurality of low-sensitivity pixels that are arranged in a matrix in gaps between the plurality of high-sensitivity pixels, and perform a photoelectric conversion at a lower sensitivity than the predetermined sensitivity; and a signal processor that generates a pixel signal by (i) detecting a difference signal between a signal from the plurality of high-sensitivity pixels and a signal from the plurality of low-sensitivity pixels, and (ii) correcting the signal from the plurality of high-sensitivity pixels using the difference signal.

Abstract: A solid-state imaging apparatus includes a pixel array, a column processor, and a test signal generating circuit that generates a first digital signal for testing purposes. The test signal generating circuit generates the first digital signal within one horizontal scanning period. The column processor converts a first analog signal, that is converted from the first digital signal, to a second digital signal within the one horizontal scanning period.

Abstract: A solid-state imaging device includes: a pixel including a photoelectric converter that generates a charge and a charge accumulator that converts the charge into a voltage; a controller that causes the pixel to perform exposure in a first exposure mode and convert the charge into the voltage with a first gain to output a first pixel signal, and causes the pixel to perform exposure in a second exposure mode and convert the charge into the voltage with a second gain to output a second pixel signal, the second exposure mode being shorter in exposure time than the first exposure mode, and the second gain being lower than the first gain; and a signal processor that synthesizes the second pixel signal after amplification and the first pixel signal.

Abstract: A solid-state imaging device includes: a pixel array unit in which a plurality of pixels are arranged in rows and columns; a plurality of column signal lines which are provided in one-to-one correspondence with pixel columns; a column processor including a plurality of column AD circuits provided in one-to-one correspondence with the plurality of column signal lines; a power supply variation detector which is connected to a power supply wire through which a power supply voltage is transmitted to each of the pixels, and which detects, in correspondence with pixel rows, power supply variation components attributed to variations in the power supply voltage; and a power supply variation corrector which corrects, for each of the pixel rows, a pixel signal detected by the column processor, using the power supply variation components detected by the power supply variation detector.

Abstract: An imaging device having a pixel including a photoelectric converter that converts incident light into charges, and a reset transistor having a first source, a first drain and a first gate, one of the first source and the first drain coupled to the photoelectric converter. The imaging device further including first voltage generating circuity that generates a first voltage; second voltage generating circuity that generates a second voltage, the second voltage generating circuity being different from the first voltage generating circuity; and first switching circuity that causes either the first voltage generating circuity or the second voltage generating circuity to selectively couple to the other of the first source and the first drain of the reset transistor.

Abstract: An imaging device comprising: a pixel comprising a photoelectric converter and a reset transistor having a source and a drain one of which is electrically connected to the photoelectric converter; a first voltage generating circuit for generating a first voltage; a second voltage generating circuit for generating a second voltage identical or equivalent to the first voltage; and a first switching circuit having a first input terminal electrically connected to the first voltage generating circuit, a second input terminal electrically connected to the second voltage generating circuit, a first output terminal electrically connected to the other of the source and the drain of the reset transistor. The first switching circuit electrically connects one of the first and second input terminals to the first output terminal selectively in a period when the photoelectric converter is reset. The photoelectric converter is reset by use of the first voltage or the second voltage.

Abstract: A solid-state imaging device includes: a plurality of unit cells each including at least one light receiving unit and an amplifying transistor which outputs an amplified signal corresponding to an amount of the signal charge photoelectrically converted by the light receiving unit; a plurality of vertical signal lines each for receiving an output signal from the amplifying transistor; a pixel power supply line for supplying a power supply voltage to the amplifying transistor; a plurality of constant current source transistors each connected to a different one of the vertical signal lines; and a bias circuit which controls an amount of current to be supplied to each of the constant current source transistors, based on a variation in the power supply voltage.

Abstract: An imaging device comprising: a pixel comprising a photoelectric converter and a reset transistor having a source and a drain one of which is electrically connected to the photoelectric converter; a first voltage generating circuit for generating a first voltage; a second voltage generating circuit for generating a second voltage identical or equivalent to the first voltage; and a first switching circuit having a first input terminal electrically connected to the first voltage generating circuit, a second input terminal electrically connected to the second voltage generating circuit, a first output terminal electrically connected to the other of the source and the drain of the reset transistor. The first switching circuit electrically connects one of the first and second input terminals to the first output terminal selectively in a period when the photoelectric converter is reset. The photoelectric converter is reset by use of the first voltage or the second voltage.

Abstract: A solid-state imaging device includes: a plurality of unit cells each including at least one light receiving unit and an amplifying transistor which outputs an amplified signal corresponding to an amount of the signal charge photoelectrically converted by the light receiving unit; a plurality of vertical signal lines each for receiving an output signal from the amplifying transistor; a pixel power supply line for supplying a power supply voltage to the amplifying transistor; a plurality of constant current source transistors each connected to a different one of the vertical signal lines; and a bias circuit which controls an amount of current to be supplied to each of the constant current source transistors, based on a variation in the power supply voltage.

Abstract: In each stage, a digital signal corresponding to a portion of bits is generated from an input analog signal, an analog reference signal is generated by a DA conversion portion (7, 8) based on the digital signal, and a remainder operation on the input analog signal is performed by a remainder operation portion (9). A test can be performed by supplying a test signal in place of the input analog signal. A control portion (14a) performs control, in a test mode, to stop supply of the input analog signal to the remainder operation portion and stop the reference voltage selection of the DA conversion portion based on the digital signal, while performing reference voltage selection based on a DA conversion control signal for use in testing, thereby supplying the remainder operation portion with the test signal composed of predetermined one of the reference voltages, in place of the input analog signal, and the analog reference signal.

Abstract: In each stage, a digital signal corresponding to a portion of bits is generated from an input analog signal, an analog reference signal is generated by a DA conversion portion (7, 8) based on the digital signal, and a remainder operation on the input analog signal is performed by a remainder operation portion (9). A test can be performed by supplying a test signal in place of the input analog signal. A control portion (14a) performs control, in a test mode, to stop supply of the input analog signal to the remainder operation portion and stop the reference voltage selection of the DA conversion portion based on the digital signal, while performing reference voltage selection based on a DA conversion control signal for use in testing, thereby supplying the remainder operation portion with the test signal composed of predetermined one of the reference voltages, in place of the input analog signal, and the analog reference signal.

Abstract: A reference voltage generation circuit of the present invention includes: a reference voltage generation part 12 that is connected between a first reference voltage terminal VRT and a second reference voltage terminal VRB and that generates a plurality of reference voltages when being supplied with a power supply current from the first and second reference voltage terminals; capacitors 13a, 13b for storing charge that are connected to the first and second reference voltage terminals, respectively; a reference voltage detection circuit 16 that detects voltage values at the first and second reference voltage terminals; current control circuits 11a, 11b that control a magnitude of a power supply current that is allowed to flow through the reference voltage generation part so that the first and second reference voltage terminals are kept at predetermined voltage values, in accordance with the voltage values detected by the reference voltage detection circuit; and switching parts 14a to 14d that switch the connect

Abstract: In each of a plurality of stages, an input analog signal is quantized, so that a digital signal corresponding to each part of bits is generated. ADA conversion portion generates an analog reference signal based on the digital signal, and a remainder operation portion performs addition/subtraction and amplification by a predetermined factor with respect to the input analog signal. Then, the signal thus obtained is supplied to a subsequent stage. The DA conversion portion in the first stage where A/D conversion of a plurality of bits is performed includes primary voltage supply portions capable of outputting a reference voltage at one of a plurality of levels, and an auxiliary voltage supply portion capable of outputting a reference voltage at an auxiliary level different from the above-described level. The respective voltage supply portions selectively output the reference voltages based on a digital signal generated by an AD conversion portion.