Abstract: The equalizer has a first differential pair having a first transistor and a second transistor and a second differential pair having a third transistor and a fourth transistor. A first terminal of the first transistor and a first terminal of the third transistor are connected to each other, and a first terminal of the second transistor and a first terminal of the fourth transistor are connected to each other, so that the first differential pair and the second differential pair have common input terminals. Also, resistors are respectively connected to second terminals of the first, second, third, and fourth transistors, a first zero point generation circuit is connected between the second terminal of the first transistor and the second terminal of the second transistor, and a second zero point generation circuit is connected between the second terminal of the third transistor and the second terminal of the fourth transistor.

Abstract: Provided is an electric signal transmission device which corrects a data error caused by data transition in a pulse amplitude modulation signal to increase an EYE width. The electric signal transmission device can operate as follows: A data pattern determined by an equalizer and a phase relationship between data and a clock detected by a phase detector are used to calculate a correction amount according to the data pattern and the phase relationship, and the received data is corrected to a correct value by adding a correction amount in a data transition direction.

Abstract: An equalizing device has: a low-frequency zero-point circuit having a zero point in a low-frequency band of a before-equalization frequency characteristic of a communication medium; a high-frequency zero-point circuit having a zero point in a high-frequency band of the before-equalization frequency characteristic of the communication medium; and an intermediate-frequency zero-point circuit having a zero point in an intermediate-frequency band present between the low-frequency band and the high-frequency band, wherein an inclination of a waveform of the before-equalization frequency characteristic of the communication medium changes in the intermediate-frequency band; wherein the equalizing device equalizes the signal transmitted through the communication medium so as to restrain an amount of change in an inclination of a waveform of the after-equalization frequency characteristic.

Abstract: Provided is an electric signal transmission device which corrects a data error caused by data transition in a pulse amplitude modulation signal to increase an EYE width. The electric signal transmission device can operate as follows: A data pattern determined by an equalizer and a phase relationship between data and a clock detected by a phase detector are used to calculate a correction amount according to the data pattern and the phase relationship, and the received data is corrected to a correct value by adding a correction amount in a data transition direction.

Abstract: An equalizing device has: a low-frequency zero-point circuit having a zero point in a low-frequency band of a before-equalization frequency characteristic of a communication medium; a high-frequency zero-point circuit having a zero point in a high-frequency band of the before-equalization frequency characteristic of the communication medium; and an intermediate-frequency zero-point circuit having a zero point in an intermediate-frequency band present between the low-frequency band and the high-frequency band, wherein an inclination of a waveform of the before-equalization frequency characteristic of the communication medium changes in the intermediate-frequency band; wherein the equalizing device equalizes the signal transmitted through the communication medium so as to restrain an amount of change in an inclination of a waveform of the after-equalization frequency characteristic.

Abstract: A decision feedback equalizer of an electric signal transmission apparatus has an average peak value determiner that receives an output of an adder and a threshold value set by a program. An average peak value of the output of the adder), compares a magnitude relation of the detected average peak value and the threshold value, increases the reference value of the output of a reference value generation circuit from an initial value set by the program and causes resolutions of DACs to become coarse from the initial value, when the average peak value is larger than the threshold value, and decreases the reference value of the output of the reference value generation circuit from the initial value set by the program and causes the resolutions of the DACs to become fine from the initial value, when the average peak value is smaller than the threshold value.

Abstract: A decision feedback equalizer of an electric signal transmission apparatus has an average peak value determiner that receives an output of an adder and a threshold value set by a program. An average peak value of the output of the adder), compares a magnitude relation of the detected average peak value and the threshold value, increases the reference value of the output of a reference value generation circuit from an initial value set by the program and causes resolutions of DACs to become coarse from the initial value, when the average peak value is larger than the threshold value, and decreases the reference value of the output of the reference value generation circuit from the initial value set by the program and causes the resolutions of the DACs to become fine from the initial value, when the average peak value is smaller than the threshold value.

Abstract: A phase detector, which forms a semiconductor device, detects a phase difference between a reference signal and a feedback signal obtained by feeding back an output signal of an oscillator, and generates a phase difference value indicating a value in accordance with the phase difference. An amplifier amplifies the phase difference value at a gain determined in accordance with a control signal from outside the device. A filter smoothes an output value of the amplifier. The oscillator controls a frequency of the output signal in accordance with an output value of the filter.

Abstract: The transmitter synthesizes amplitude and phase components and calibrates a delay mismatch between amplitude and phase components with high accuracy at high speed. The transmitter has: a digital-to-analog converter (DAC) and a low-pass filter (LPF) in its amplitude-signal path; and a phase modulator operable to convert up a phase component into an RF component in its phase-signal path. In an operation of delay calibration, a test input signal is supplied to a delay-calibrating unit in the amplitude-signal path, and the delay-calibrating unit provides a test input signal to DAC. Then, LPF generates a test output signal. The delay-calibrating unit detects a delay of the test output signal relative to the test input signal, calibrates an amplitude signal delay in a range from the input of the delay-calibrating unit to the output of LPF, reduces the difference between amplitude and phase signal delays of the phase modulator in the phase-signal path.

Abstract: A quadrature modulator has first to fourth transistors, a first node, a second node, and a first output node. A non-inversion in-phase analog signal, an inversion in-phase analog signal, a non-inversion quadrature analog signal, and an inversion quadrature analog signal are supplied to input electrodes of the first to fourth transistors, respectively. Control electrodes of the first to fourth transistors respond to a non-inversion in-phase RF signal, an inversion in-phase RF signal, a non-inversion quadrature RF signal, and an inversion quadrature RF signal, respectively. Output electrodes of the first and second transistors are coupled to the first node, and output electrodes of the third and fourth transistors are coupled to the second node. A first high-pass filter is coupled between the first node and the first output node, and a second high-pass filter is coupled between the second node and the first output node.

Abstract: A quadrature modulator has first to fourth transistors, a first node, a second node, and a first output node. A non-inversion in-phase analog signal, an inversion in-phase analog signal, a non-inversion quadrature analog signal, and an inversion quadrature analog signal are supplied to input electrodes of the first to fourth transistors, respectively. Control electrodes of the first to fourth transistors respond to a non-inversion in-phase RF signal, an inversion in-phase RF signal, a non-inversion quadrature RF signal, and an inversion quadrature RF signal, respectively. Output electrodes of the first and second transistors are coupled to the first node, and output electrodes of the third and fourth transistors are coupled to the second node. A first high-pass filter is coupled between the first node and the first output node, and a second high-pass filter is coupled between the second node and the first output node.

Abstract: The transmitter synthesizes amplitude and phase components and calibrates a delay mismatch between amplitude and phase components with high accuracy at high speed. The transmitter has: a digital-to-analog converter (DAC) and a low-pass filter (LPF) in its amplitude-signal path; and a phase modulator operable to convert up a phase component into an RF component in its phase-signal path. In an operation of delay calibration, a test input signal is supplied to a delay-calibrating unit in the amplitude-signal path, and the delay-calibrating unit provides a test input signal to DAC. Then, LPF generates a test output signal. The delay-calibrating unit detects a delay of the test output signal relative to the test input signal, calibrates an amplitude signal delay in a range from the input of the delay-calibrating unit to the output of LPF, reduces the difference between amplitude and phase signal delays of the phase modulator in the phase-signal path.

Abstract: The present invention provides a semiconductor integrated circuit capable of reducing a chip occupied area and reducing variations in control gain of a digitally controlled oscillator. The semiconductor integrated circuit is equipped with the digitally controlled oscillator. The digitally controlled oscillator comprises oscillation transistors and a resonant circuit. The resonant circuit comprises inductances, a frequency coarse-tuning variable capacitor array and a frequency fine-tuning variable capacitor array. The frequency coarse-tuning variable capacitor array comprises a plurality of coarse-tuning capacitor unit cells. The frequency fine-tuning variable capacitor array comprises a plurality of fine-tuning capacitor unit cells. The capacitance values of the coarse-tuning capacitor unit cells of the frequency coarse-tuning variable capacitor array are set in accordance with a binary weight 2M?1.

Abstract: A pulse generator for UWB transmission, lower power consumption, and suppression of LO leakage by nonuse of the LO signal. The pulse generator includes a clock generator (CLK) for giving clock of a predetermined period; a delay circuit (DLY) equipped with a function of controlling a delay time and for delaying the clock; a square-wave pulse generation circuit (SWPG) that receives information being spread by a spread code and modulates phases of square wave pulses that have a pulse width corresponding to a differential delay for one stage of the delay circuit; and an amplitude control unit (AMPC) that outputs an impulse sequence having the pulse width of the square wave in a predetermined amplitude and combines the impulses; and outputs pulses that have a predetermined envelope form.

Abstract: Provided is a semiconductor integrated circuit, in which a transmit pulse having an impulse waveform is produced using pull-up and pull-down currents of the charge pumps of pattern-generating cells of the pattern generator. During the first calibrating operation of semiconductor integrated circuit, the variation in amplitude of the transmit pulse is detected. At least one of pull-up and pull-down currents of the charge pumps is controlled according to a first calibration control signal responsive to the result of detection of the amplitude. During the second calibrating operation, the fluctuation in DC level just after producing of a repeat pulse of the transmit pulse is also detected. Imbalance between the pull-up and pull-down currents of the charge pumps are lowered according to a second calibration control signal responsive to the result of detection of the DC level fluctuation.

Abstract: The object is simplification of a configuration in a pulse generator for UWB transmission, lower power consumption, and suppression of LO leakage by nonuse of the LO signal.

Abstract: An ultra-wideband transmitter is provided which can reduce a leak of a local signal into a transmitted signal with a pulse train output from an antenna in UWB-IR communication. The transmitter comprises a pulse generator 0140 for generating a pulse signal having a pulse train of pulses produced intermittently according to data to be transmitted, an oscillator 0120 for producing a local signal, a frequency converter 0130 to which the pulse signal output from the pulse generator and the local signal output from the oscillator are input, and for frequency-converting the pulse signal to output a RF signal, an amplifier 0110 for amplifying the RF signal output from the frequency converter, and an antenna 0000 for emitting the RF signal output from the amplifier in the air. In a period corresponding to a pause period of the pulses produced intermittently, a leak of the local signal into the RF signal output from the antenna is reduced using a control signal 0300.