Patents by Inventor Takayo Kobayashi

Takayo Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240116589
    Abstract: An operation pedal system that is installed in a straddle-type vehicle includes an operation pedal having an arm portion and a pedal portion, and a tread surface forming member that is attached to the pedal portion to form a first tread surface above the pedal portion that receives a stepping force when a stepping operation is performed on the operation pedal. In the operation pedal system, the tread surface forming member is separate from the operation pedal, and the tread surface forming member has a body portion having a tread surface forming surface forming the first tread surface on an upper surface, and an attachment mechanism provided on the body portion for detachably attaching the tread surface forming member to the pedal portion.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 11, 2024
    Applicant: SUZUKI MOTOR CORPORATION
    Inventors: Takayo YAMAMOTO, Koji KOBAYASHI, Hideaki FUKUSHIMA
  • Patent number: 7898084
    Abstract: A semiconductor device is disclosed, which includes a first interlayer insulating film, a lower-layer interconnection in a first groove in the first film, a second interlayer insulating film over the first film, having a normal via hole opening to the lower-layer interconnection, a normal plug in the normal hole, a third interlayer insulating film over the second film, having a second groove opening to the normal plug, an upper-layer interconnection in the second groove, and a first dummy plug in a first dummy via hole in the second film, the first dummy via hole opening to one of the lower-layer and upper-layer interconnections, wherein a short side of the first dummy plug is larger than a minimum width of a minimum width interconnection and smaller than a minimum diameter of a minimum diameter via hole and a long side is larger than a shortest length of a shortest length interconnection.
    Type: Grant
    Filed: January 18, 2006
    Date of Patent: March 1, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayo Kobayashi, Takamasa Usui
  • Patent number: 7833912
    Abstract: According to an aspect of the present invention, there is provided a semiconductor device including a semiconductor substrate which includes a number of chip areas, a processed film which is formed on the semiconductor substrate, and a ring-shaped pattern which is formed on the processed film and along a peripheral portion of the semiconductor substrate.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: November 16, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayo Kobayashi, Tomohiro Oki
  • Publication number: 20100244254
    Abstract: A semiconductor device is disclosed, which includes a first interlayer insulating film, a lower-layer interconnection in a first groove in the first film, a second interlayer insulating film over the first film, having a normal via hole opening to the lower-layer interconnection, a normal plug in the normal hole, a third interlayer insulating film over the second film, having a second groove opening to the normal plug, an upper-layer interconnection in the second groove, and a first dummy plug in a first dummy via hole in the second film, the first dummy via hole opening to one of the lower-layer and upper-layer interconnections, wherein a short side of the first dummy plug is larger than a minimum width of a minimum width interconnection and smaller than a minimum diameter of a minimum diameter via hole and a long side is larger than a shortest length of a shortest length interconnection.
    Type: Application
    Filed: March 24, 2010
    Publication date: September 30, 2010
    Inventors: Takayo Kobayashi, Takamasa Usui
  • Patent number: 7572717
    Abstract: According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including forming on a semiconductor substrate an insulating film having a recessed portion in a surface thereof, forming on the insulating film a first metal film so as to fill up the recessed portion, forming on the first metal film a second metal film having lower vacancy density than that of the first metal film, forming on the second metal film a compression stress applying film which applies compression stress to the first metal film through the second metal film when heat treatment is applied, performing heat treatment on the first metal film, the second metal film and the compression stress applying film, and removing the second metal film and the first metal film except a portion thereof filling up the recessed portion to thereby form a wiring in the recessed portion.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: August 11, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayo Kobayashi, Kentaro Imamizu
  • Publication number: 20070254463
    Abstract: According to an aspect of the present invention, there is provided a semiconductor device including a semiconductor substrate which includes a number of chip areas, a processed film which is formed on the semiconductor substrate, and a ring-shaped pattern which is formed on the processed film and along a peripheral portion of the semiconductor substrate.
    Type: Application
    Filed: April 27, 2007
    Publication date: November 1, 2007
    Inventors: Takayo Kobayashi, Tomohiro Oki
  • Publication number: 20070059924
    Abstract: According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including forming on a semiconductor substrate an insulating film having a recessed portion in a surface thereof, forming on the insulating film a first metal film so as to fill up the recessed portion, forming on the first metal film a second metal film having lower vacancy density than that of the first metal film, forming on the second metal film a compression stress applying film which applies compression stress to the first metal film through the second metal film when heat treatment is applied, performing heat treatment on the first metal film, the second metal film and the compression stress applying film, and removing the second metal film and the first metal film except a portion thereof filling up the recessed portion to thereby form a wiring in the recessed portion.
    Type: Application
    Filed: July 31, 2006
    Publication date: March 15, 2007
    Inventors: Takayo Kobayashi, Kentaro Imamizu
  • Publication number: 20060170109
    Abstract: A semiconductor device is disclosed, which includes a first interlayer insulating film, a lower-layer interconnection in a first groove in the first film, a second interlayer insulating film over the first film, having a normal via hole opening to the lower-layer interconnection, a normal plug in the normal hole, a third interlayer insulating film over the second film, having a second groove opening to the normal plug, an upper-layer interconnection in the second groove, and a first dummy plug in a first dummy via hole in the second film, the first dummy via hole opening to one of the lower-layer and upper-layer interconnections, wherein a short side of the first dummy plug is larger than a minimum width of a minimum width interconnection and smaller than a minimum diameter of a minimum diameter via hole and a long side is larger than a shortest length of a shortest length interconnection.
    Type: Application
    Filed: January 18, 2006
    Publication date: August 3, 2006
    Inventors: Takayo Kobayashi, Takamasa Usui