Patents by Inventor Takayoshi Andou

Takayoshi Andou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9136262
    Abstract: A semiconductor device includes a transistor having a gate electrode, a first electrode, and a second electrode and first and second protection circuits each having one end commonly connected to the gate electrode and the other end connected to the first and second electrodes, respectively. The first and second protection circuits are formed in first and second polysilicon layers, respectively, formed separately on a single field insulating film.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: September 15, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Takayoshi Andou
  • Publication number: 20150155272
    Abstract: A semiconductor device includes a transistor having a gate electrode, a first electrode, and a second electrode and first and second protection circuits each having one end commonly connected to the gate electrode and the other end connected to the first and second electrodes, respectively. The first and second protection circuits are formed in first and second polysilicon layers, respectively, formed separately on a single field insulating film.
    Type: Application
    Filed: February 4, 2015
    Publication date: June 4, 2015
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Takayoshi ANDOU
  • Patent number: 8981424
    Abstract: A semiconductor device includes a transistor having a gate electrode, a first electrode, and a second electrode and first and second protection circuits each having one end commonly connected to the gate electrode and the other end connected to the first and second electrodes, respectively. The first and second protection circuits are formed in first and second polysilicon layers, respectively, formed separately on a single field insulating film.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: March 17, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Takayoshi Andou
  • Patent number: 7867857
    Abstract: An improved coupling stability between the source region and the source electrode of the transistor is achieved. In the method for manufacturing the MOSFET, the p-type base region is formed in a semiconductor layer, and after the p-type base region is formed in the surface portion of the n+ type source region, the higher concentration source region extending from the side edge of the n+ type source region to the lateral side of the n+ type source region is formed in the surface portion of the p-type base region. Then, the source electrode coupled to the higher concentration source region is formed. This allows providing an improved coupling stability between the source electrode and the source region when a misalignment is occurred in the location for forming the source electrode during the formation of the source electrode to be coupled to the first source region.
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: January 11, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Takayoshi Andou, Kenya Kobayashi
  • Publication number: 20100006929
    Abstract: A semiconductor device contains a semiconductor substrate having a p-type semiconductor layer and an n-type channel layer formed thereon; gate trenches extended through the channel layer so as to reach the p-type semiconductor layer; oxide films formed over the bottom and inner wall of the gate trenches, the oxide films being formed thicker over the bottom of the gate trenches than over the inner wall; gate electrodes formed so as to fill the gate trenches; n-type regions formed at the bottom of the gate trenches, and containing arsenic as a major n-type impurity component; low concentration p-type regions formed under the n-type regions, and having a low p-type impurity concentration; and a drain electrode formed on the back surface of the substrate.
    Type: Application
    Filed: July 2, 2009
    Publication date: January 14, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Takayoshi Andou
  • Publication number: 20080111168
    Abstract: An improved coupling stability between the source region and the source electrode of the transistor is achieved. In the method for manufacturing the MOSFET, the p-type base region is formed in a semiconductor layer, and after the p-type base region is formed in the surface portion of the n+ type source region, the higher concentration source region extending from the side edge of the n+ type source region to the lateral side of the n+ type source region is formed in the surface portion of the p-type base region. Then, the source electrode coupled to the higher concentration source region is formed. This allows providing an improved coupling stability between the source electrode and the source region when a misalignment is occurred in the location for forming the source electrode during the formation of the source electrode to be coupled to the first source region.
    Type: Application
    Filed: November 7, 2007
    Publication date: May 15, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Takayoshi ANDOU, Kenya KOBAYASHI
  • Patent number: 6400026
    Abstract: In a semiconductor device, an active region is formed on a semiconductor substrate. An electrode layer is directly formed on the active region and serves as a bonding pad. The electrode layer is mainly formed by an Al alloy layer containing Cu.
    Type: Grant
    Filed: June 26, 2000
    Date of Patent: June 4, 2002
    Assignee: NEC Corporation
    Inventors: Takayoshi Andou, Hitoshi Ninomiya, Kinya Ohtani